const (
BaseTypeInt = 1 << iota
BaseTypeUint
BaseTypeFloat
)
const (
DefaultArngs = ArngShape(iota) // DefaultArngs indicates that vector register arguments have the same bit width.
NarrowArngs // NarrowArngs signifies that the destination vector register is half the bit width of the source, used in instructions like XTN/XTN2.
LongArngs // LongArngs indicates that the destination vector register is double the bit width of the source, seen in instructions like UXTL/UXTL2.
WideArngs // WideArngs applies when the second argument vector register is half the bit width of the first argument or the result, as in UADDW.
UnsupportedArngs // UnsupportedArngs indicates instructions whose arrangement shape is not yet supported by simdgen.
)
func Load(path string) ([]*unify.Value, error)
Load loads ARM64 instruction definitions from XML files at given path and returns them as unify values.
ArngShape makes certain vreg operands half or double bits wide.
type ArngShape int
Arrangement defines the properties of a vector arrangement.
type Arrangement struct {
// contains filtered or unexported fields
}
BaseTypeSet allows to specify the type set of values independent of arrangement's size, e.g.: - Float (instruction used for floating point values in lanes), - Uint (instruction used only for unsigned integer values in lanes with any arrangement), - Float|Int|Uint (e.g. VMOV V1.S[i], V0.S[j]: copy i-th lane from src vreg to j-th lane of dst vreg: basically don't care about base type).
type BaseTypeSet int
func (t BaseTypeSet) String() string
Instruction represents a parsed ARM64 instruction with domain logic
type Instruction struct {
xmlspec.Instruction // Embedded XML data from xmlspec
// contains filtered or unexported fields
}
func ParseInstructions(path string) ([]*Instruction, error)
ParseInstructions loads and parses ARM64 instruction definitions from XML files at given path.
func (instruction *Instruction) ArngShape() ArngShape
ArngShape returns the arrangement shape. Returns UnsupportedArngs for instructions we don't support yet - those will not be emitted. If we were not able to classify the instruction, panic to prevent wrong yaml generation.
func (instruction *Instruction) Arrangements() ([]Arrangement, ArngShape)
Arrangements collects valid arrangement/type specifiers for the instruction
func (instruction *Instruction) BaseTypeSet() BaseTypeSet
BaseTypeSet determines if an instruction operates on integers or floats
func (instruction *Instruction) Bitwise() bool
Bitwise returns true if the instruction is a bitwise operation by detecting "Bitwise " prefix in the brief description
func (instruction *Instruction) Brief() string
Brief returns the brief description from XML
func (instruction *Instruction) Documentation() string
Documentation extracts detailed instruction documentation from the XML
func (instruction *Instruction) EmitAll() []*unify.Value
EmitAll generates instruction definitions for all arrangements of this instruction. Returns nil for instructions with UnsupportedArngs.
func (instruction *Instruction) InstrClass() string
InstrClass returns the instruction Class from docvars
func (instruction *Instruction) IsAlias() bool
IsAlias returns true if this instruction is an alias of another instruction
func (instruction *Instruction) Mnemonic() string
Mnemonic extracts the mnemonic from docvars
func (instruction *Instruction) ResultInArg0() bool
ResultInArg0 determines if result shares register with first argument. This occurs when the destination register is also read as an input operand.
Operand represents an arm64 instruction operand instantiated for concrete arrangement.
type Operand struct {
Type OperandType
Class string // "vreg", "greg", "immediate"
BaseType string // Base type ("int", "uint", "float")
ElemBits int // Element bits (for vectors)
Bits int // Total bits
Lanes int // Number of lanes (for vectors)
ImmMax int // Immediate max value (for immediates)
// The operand's role. Possible values:
// - "destination": the output register
// - "original": the original SSA value of "destination" (for resultInArg0 instructions)
// - ends with "_i": vector element index: should get ImmMax = lanes-1
// - "op0", "op1", ...: input registers
// - other strings: immediate names (e.g. "immshift", "amount", "immzero")
Role string
ListNumber int // List number for register list (e.g., useful for TBL/TBX instructions)
AsmPos int // Assembly position (usually 0 for the destination register, 1+ for inputs).
}
func (op *Operand) Emit() *unify.Value
Emit generates the unify.Value representation of this operand
OperandType defines the type of an operand for ARM64 instruction generation.
type OperandType int
const (
OperandVReg OperandType = iota // Vector register
OperandGReg // General register
OperandImm // Immediate
OperandVElem // Vector element (e.g., <Vm>.H[<index>]): early-lowered into immediate + vreg with same AsmPos
OperandList // List operand (e.g., { <Vn>.16B, <Vn+1>.16B }): early-lowered into vreg with ListNumber
)
func (t OperandType) String() string