1// Copyright 2016 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5// Lowering arithmetic
6(Add(Ptr|32|16|8) ...) => (ADDL ...)
7(Add(32|64)F ...) => (ADDS(S|D) ...)
8(Add32carry ...) => (ADDLcarry ...)
9(Add32withcarry ...) => (ADCL ...)
10
11(Sub(Ptr|32|16|8) ...) => (SUBL ...)
12(Sub(32|64)F ...) => (SUBS(S|D) ...)
13(Sub32carry ...) => (SUBLcarry ...)
14(Sub32withcarry ...) => (SBBL ...)
15
16(Mul(32|16|8) ...) => (MULL ...)
17(Mul(32|64)F ...) => (MULS(S|D) ...)
18(Mul32uhilo ...) => (MULLQU ...)
19
20(Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
21(Select1 (Mul32uover x y)) => (SETO (Select1 <types.TypeFlags> (MULLU x y)))
22
23(Avg32u ...) => (AVGLU ...)
24
25(Div(32|64)F ...) => (DIVS(S|D) ...)
26(Div(32|32u|16|16u) ...) => (DIV(L|LU|W|WU) ...)
27(Div8 x y) => (DIVW (SignExt8to16 x) (SignExt8to16 y))
28(Div8u x y) => (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))
29
30(Hmul(32|32u) ...) => (HMUL(L|LU) ...)
31
32(Mod(32|32u|16|16u) ...) => (MOD(L|LU|W|WU) ...)
33(Mod8 x y) => (MODW (SignExt8to16 x) (SignExt8to16 y))
34(Mod8u x y) => (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y))
35
36(And(32|16|8) ...) => (ANDL ...)
37(Or(32|16|8) ...) => (ORL ...)
38(Xor(32|16|8) ...) => (XORL ...)
39
40(Neg(32|16|8) ...) => (NEGL ...)
41(Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
42(Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
43
44(Com(32|16|8) ...) => (NOTL ...)
45
46// Lowering boolean ops
47(AndB ...) => (ANDL ...)
48(OrB ...) => (ORL ...)
49(Not x) => (XORLconst [1] x)
50
51// Lowering pointer arithmetic
52(OffPtr [off] ptr) => (ADDLconst [int32(off)] ptr)
53
54(Bswap32 ...) => (BSWAPL ...)
55(Bswap16 x) => (ROLWconst [8] x)
56
57(Sqrt ...) => (SQRTSD ...)
58(Sqrt32 ...) => (SQRTSS ...)
59
60(Ctz8 x) => (BSFL (ORLconst <typ.UInt32> [0x100] x))
61(Ctz8NonZero ...) => (BSFL ...)
62(Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [0x10000] x))
63(Ctz16NonZero ...) => (BSFL ...)
64(Ctz32 ...) => (LoweredCtz32 ...)
65(Ctz32NonZero ...) => (BSFL ...)
66(Ctz64On32 ...) => (LoweredCtz64 ...)
67
68// Lowering extension
69(SignExt8to16 ...) => (MOVBLSX ...)
70(SignExt8to32 ...) => (MOVBLSX ...)
71(SignExt16to32 ...) => (MOVWLSX ...)
72
73(ZeroExt8to16 ...) => (MOVBLZX ...)
74(ZeroExt8to32 ...) => (MOVBLZX ...)
75(ZeroExt16to32 ...) => (MOVWLZX ...)
76
77(Signmask x) => (SARLconst x [31])
78(Zeromask <t> x) => (XORLconst [-1] (SBBLcarrymask <t> (CMPLconst x [1])))
79(Slicemask <t> x) => (SARLconst (NEGL <t> x) [31])
80
81// Lowering truncation
82// Because we ignore high parts of registers, truncates are just copies.
83(Trunc16to8 ...) => (Copy ...)
84(Trunc32to8 ...) => (Copy ...)
85(Trunc32to16 ...) => (Copy ...)
86
87// Lowering float-int conversions
88(Cvt32to32F ...) => (CVTSL2SS ...)
89(Cvt32to64F ...) => (CVTSL2SD ...)
90
91(Cvt32Fto32 ...) => (CVTTSS2SL ...)
92(Cvt64Fto32 ...) => (CVTTSD2SL ...)
93
94(Cvt32Fto64F ...) => (CVTSS2SD ...)
95(Cvt64Fto32F ...) => (CVTSD2SS ...)
96
97(Round32F ...) => (Copy ...)
98(Round64F ...) => (Copy ...)
99
100(CvtBoolToUint8 ...) => (Copy ...)
101
102// Lowering shifts
103// Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
104// result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
105(Lsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
106(Lsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
107(Lsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
108
109(Lsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
110(Lsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
111(Lsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SHLL <t> x y)
112
113(Rsh32Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [32])))
114(Rsh16Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [16])))
115(Rsh8Ux(32|16|8) <t> x y) && !shiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(L|W|B)const y [8])))
116
117(Rsh32Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRL <t> x y)
118(Rsh16Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRW <t> x y)
119(Rsh8Ux(32|16|8) <t> x y) && shiftIsBounded(v) => (SHRB <t> x y)
120
121// Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
122// We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
123
124(Rsh32x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [32])))))
125(Rsh16x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [16])))))
126(Rsh8x(32|16|8) <t> x y) && !shiftIsBounded(v) => (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMP(L|W|B)const y [8])))))
127
128(Rsh32x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARL x y)
129(Rsh16x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARW x y)
130(Rsh8x(32|16|8) <t> x y) && shiftIsBounded(v) => (SARB x y)
131
132// constant shifts
133// generic opt rewrites all constant shifts to shift by Const64
134(Lsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SHLLconst x [int32(c)])
135(Rsh32x64 x (Const64 [c])) && uint64(c) < 32 => (SARLconst x [int32(c)])
136(Rsh32Ux64 x (Const64 [c])) && uint64(c) < 32 => (SHRLconst x [int32(c)])
137(Lsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SHLLconst x [int32(c)])
138(Rsh16x64 x (Const64 [c])) && uint64(c) < 16 => (SARWconst x [int16(c)])
139(Rsh16Ux64 x (Const64 [c])) && uint64(c) < 16 => (SHRWconst x [int16(c)])
140(Lsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SHLLconst x [int32(c)])
141(Rsh8x64 x (Const64 [c])) && uint64(c) < 8 => (SARBconst x [int8(c)])
142(Rsh8Ux64 x (Const64 [c])) && uint64(c) < 8 => (SHRBconst x [int8(c)])
143
144// large constant shifts
145(Lsh32x64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0])
146(Rsh32Ux64 _ (Const64 [c])) && uint64(c) >= 32 => (Const32 [0])
147(Lsh16x64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0])
148(Rsh16Ux64 _ (Const64 [c])) && uint64(c) >= 16 => (Const16 [0])
149(Lsh8x64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0])
150(Rsh8Ux64 _ (Const64 [c])) && uint64(c) >= 8 => (Const8 [0])
151
152// large constant signed right shift, we leave the sign bit
153(Rsh32x64 x (Const64 [c])) && uint64(c) >= 32 => (SARLconst x [31])
154(Rsh16x64 x (Const64 [c])) && uint64(c) >= 16 => (SARWconst x [15])
155(Rsh8x64 x (Const64 [c])) && uint64(c) >= 8 => (SARBconst x [7])
156
157// rotates
158(RotateLeft32 ...) => (ROLL ...)
159(RotateLeft16 ...) => (ROLW ...)
160(RotateLeft8 ...) => (ROLB ...)
161// constant rotates
162(ROLL x (MOVLconst [c])) => (ROLLconst [c&31] x)
163(ROLW x (MOVLconst [c])) => (ROLWconst [int16(c&15)] x)
164(ROLB x (MOVLconst [c])) => (ROLBconst [int8(c&7)] x)
165
166// Lowering comparisons
167(Less32 x y) => (SETL (CMPL x y))
168(Less16 x y) => (SETL (CMPW x y))
169(Less8 x y) => (SETL (CMPB x y))
170(Less32U x y) => (SETB (CMPL x y))
171(Less16U x y) => (SETB (CMPW x y))
172(Less8U x y) => (SETB (CMPB x y))
173// Use SETGF with reversed operands to dodge NaN case
174(Less64F x y) => (SETGF (UCOMISD y x))
175(Less32F x y) => (SETGF (UCOMISS y x))
176
177(Leq32 x y) => (SETLE (CMPL x y))
178(Leq16 x y) => (SETLE (CMPW x y))
179(Leq8 x y) => (SETLE (CMPB x y))
180(Leq32U x y) => (SETBE (CMPL x y))
181(Leq16U x y) => (SETBE (CMPW x y))
182(Leq8U x y) => (SETBE (CMPB x y))
183// Use SETGEF with reversed operands to dodge NaN case
184(Leq64F x y) => (SETGEF (UCOMISD y x))
185(Leq32F x y) => (SETGEF (UCOMISS y x))
186
187(Eq32 x y) => (SETEQ (CMPL x y))
188(Eq16 x y) => (SETEQ (CMPW x y))
189(Eq8 x y) => (SETEQ (CMPB x y))
190(EqB x y) => (SETEQ (CMPB x y))
191(EqPtr x y) => (SETEQ (CMPL x y))
192(Eq64F x y) => (SETEQF (UCOMISD x y))
193(Eq32F x y) => (SETEQF (UCOMISS x y))
194
195(Neq32 x y) => (SETNE (CMPL x y))
196(Neq16 x y) => (SETNE (CMPW x y))
197(Neq8 x y) => (SETNE (CMPB x y))
198(NeqB x y) => (SETNE (CMPB x y))
199(NeqPtr x y) => (SETNE (CMPL x y))
200(Neq64F x y) => (SETNEF (UCOMISD x y))
201(Neq32F x y) => (SETNEF (UCOMISS x y))
202
203// Lowering loads
204(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVLload ptr mem)
205(Load <t> ptr mem) && is16BitInt(t) => (MOVWload ptr mem)
206(Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) => (MOVBload ptr mem)
207(Load <t> ptr mem) && is32BitFloat(t) => (MOVSSload ptr mem)
208(Load <t> ptr mem) && is64BitFloat(t) => (MOVSDload ptr mem)
209
210// Lowering stores
211(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
212(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
213(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
214(Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
215(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
216
217// Lowering moves
218(Move [0] _ _ mem) => mem
219(Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
220(Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
221(Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
222(Move [3] dst src mem) =>
223 (MOVBstore [2] dst (MOVBload [2] src mem)
224 (MOVWstore dst (MOVWload src mem) mem))
225(Move [5] dst src mem) =>
226 (MOVBstore [4] dst (MOVBload [4] src mem)
227 (MOVLstore dst (MOVLload src mem) mem))
228(Move [6] dst src mem) =>
229 (MOVWstore [4] dst (MOVWload [4] src mem)
230 (MOVLstore dst (MOVLload src mem) mem))
231(Move [7] dst src mem) =>
232 (MOVLstore [3] dst (MOVLload [3] src mem)
233 (MOVLstore dst (MOVLload src mem) mem))
234(Move [8] dst src mem) =>
235 (MOVLstore [4] dst (MOVLload [4] src mem)
236 (MOVLstore dst (MOVLload src mem) mem))
237
238// Adjust moves to be a multiple of 4 bytes.
239(Move [s] dst src mem)
240 && s > 8 && s%4 != 0 =>
241 (Move [s-s%4]
242 (ADDLconst <dst.Type> dst [int32(s%4)])
243 (ADDLconst <src.Type> src [int32(s%4)])
244 (MOVLstore dst (MOVLload src mem) mem))
245
246// Medium copying uses a duff device.
247(Move [s] dst src mem)
248 && s > 8 && s <= 4*128 && s%4 == 0
249 && !config.noDuffDevice && logLargeCopy(v, s) =>
250 (DUFFCOPY [10*(128-s/4)] dst src mem)
251// 10 and 128 are magic constants. 10 is the number of bytes to encode:
252// MOVL (SI), CX
253// ADDL $4, SI
254// MOVL CX, (DI)
255// ADDL $4, DI
256// and 128 is the number of such blocks. See src/runtime/duff_386.s:duffcopy.
257
258// Large copying uses REP MOVSL.
259(Move [s] dst src mem) && (s > 4*128 || config.noDuffDevice) && s%4 == 0 && logLargeCopy(v, s) =>
260 (REPMOVSL dst src (MOVLconst [int32(s/4)]) mem)
261
262// Lowering Zero instructions
263(Zero [0] _ mem) => mem
264(Zero [1] destptr mem) => (MOVBstoreconst [0] destptr mem)
265(Zero [2] destptr mem) => (MOVWstoreconst [0] destptr mem)
266(Zero [4] destptr mem) => (MOVLstoreconst [0] destptr mem)
267
268(Zero [3] destptr mem) =>
269 (MOVBstoreconst [makeValAndOff(0,2)] destptr
270 (MOVWstoreconst [makeValAndOff(0,0)] destptr mem))
271(Zero [5] destptr mem) =>
272 (MOVBstoreconst [makeValAndOff(0,4)] destptr
273 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
274(Zero [6] destptr mem) =>
275 (MOVWstoreconst [makeValAndOff(0,4)] destptr
276 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
277(Zero [7] destptr mem) =>
278 (MOVLstoreconst [makeValAndOff(0,3)] destptr
279 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
280
281// Strip off any fractional word zeroing.
282(Zero [s] destptr mem) && s%4 != 0 && s > 4 =>
283 (Zero [s-s%4] (ADDLconst destptr [int32(s%4)])
284 (MOVLstoreconst [0] destptr mem))
285
286// Zero small numbers of words directly.
287(Zero [8] destptr mem) =>
288 (MOVLstoreconst [makeValAndOff(0,4)] destptr
289 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))
290(Zero [12] destptr mem) =>
291 (MOVLstoreconst [makeValAndOff(0,8)] destptr
292 (MOVLstoreconst [makeValAndOff(0,4)] destptr
293 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem)))
294(Zero [16] destptr mem) =>
295 (MOVLstoreconst [makeValAndOff(0,12)] destptr
296 (MOVLstoreconst [makeValAndOff(0,8)] destptr
297 (MOVLstoreconst [makeValAndOff(0,4)] destptr
298 (MOVLstoreconst [makeValAndOff(0,0)] destptr mem))))
299
300// Medium zeroing uses a duff device.
301(Zero [s] destptr mem)
302 && s > 16 && s <= 4*128 && s%4 == 0
303 && !config.noDuffDevice =>
304 (DUFFZERO [1*(128-s/4)] destptr (MOVLconst [0]) mem)
305// 1 and 128 are magic constants. 1 is the number of bytes to encode STOSL.
306// 128 is the number of STOSL instructions in duffzero.
307// See src/runtime/duff_386.s:duffzero.
308
309// Large zeroing uses REP STOSQ.
310(Zero [s] destptr mem)
311 && (s > 4*128 || (config.noDuffDevice && s > 16))
312 && s%4 == 0 =>
313 (REPSTOSL destptr (MOVLconst [int32(s/4)]) (MOVLconst [0]) mem)
314
315
316// Lowering constants
317(Const8 [c]) => (MOVLconst [int32(c)])
318(Const16 [c]) => (MOVLconst [int32(c)])
319(Const32 ...) => (MOVLconst ...)
320(Const(32|64)F ...) => (MOVS(S|D)const ...)
321(ConstNil) => (MOVLconst [0])
322(ConstBool [c]) => (MOVLconst [b2i32(c)])
323
324// Lowering calls
325(StaticCall ...) => (CALLstatic ...)
326(ClosureCall ...) => (CALLclosure ...)
327(InterCall ...) => (CALLinter ...)
328(TailCall ...) => (CALLtail ...)
329
330// Miscellaneous
331(IsNonNil p) => (SETNE (TESTL p p))
332(IsInBounds idx len) => (SETB (CMPL idx len))
333(IsSliceInBounds idx len) => (SETBE (CMPL idx len))
334(NilCheck ...) => (LoweredNilCheck ...)
335(GetG ...) => (LoweredGetG ...)
336(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
337(GetCallerPC ...) => (LoweredGetCallerPC ...)
338(GetCallerSP ...) => (LoweredGetCallerSP ...)
339(Addr {sym} base) => (LEAL {sym} base)
340(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAL {sym} (SPanchored base mem))
341(LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (LEAL {sym} base)
342
343// block rewrites
344(If (SETL cmp) yes no) => (LT cmp yes no)
345(If (SETLE cmp) yes no) => (LE cmp yes no)
346(If (SETG cmp) yes no) => (GT cmp yes no)
347(If (SETGE cmp) yes no) => (GE cmp yes no)
348(If (SETEQ cmp) yes no) => (EQ cmp yes no)
349(If (SETNE cmp) yes no) => (NE cmp yes no)
350(If (SETB cmp) yes no) => (ULT cmp yes no)
351(If (SETBE cmp) yes no) => (ULE cmp yes no)
352(If (SETA cmp) yes no) => (UGT cmp yes no)
353(If (SETAE cmp) yes no) => (UGE cmp yes no)
354(If (SETO cmp) yes no) => (OS cmp yes no)
355
356// Special case for floating point - LF/LEF not generated
357(If (SETGF cmp) yes no) => (UGT cmp yes no)
358(If (SETGEF cmp) yes no) => (UGE cmp yes no)
359(If (SETEQF cmp) yes no) => (EQF cmp yes no)
360(If (SETNEF cmp) yes no) => (NEF cmp yes no)
361
362(If cond yes no) => (NE (TESTB cond cond) yes no)
363
364// Write barrier.
365(WB ...) => (LoweredWB ...)
366
367(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
368(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
369(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
370
371(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem)
372(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem)
373(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem)
374
375// ***************************
376// Above: lowering rules
377// Below: optimizations
378// ***************************
379// TODO: Should the optimizations be a separate pass?
380
381// Fold boolean tests into blocks
382(NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no)
383(NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no)
384(NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no)
385(NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no)
386(NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no)
387(NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
388(NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no)
389(NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
390(NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no)
391(NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
392(NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)
393
394// Special case for floating point - LF/LEF not generated
395(NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no)
396(NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no)
397(NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no)
398(NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no)
399
400// fold constants into instructions
401(ADDL x (MOVLconst <t> [c])) && !t.IsPtr() => (ADDLconst [c] x)
402(ADDLcarry x (MOVLconst [c])) => (ADDLconstcarry [c] x)
403(ADCL x (MOVLconst [c]) f) => (ADCLconst [c] x f)
404
405(SUBL x (MOVLconst [c])) => (SUBLconst x [c])
406(SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))
407(SUBLcarry x (MOVLconst [c])) => (SUBLconstcarry [c] x)
408(SBBL x (MOVLconst [c]) f) => (SBBLconst [c] x f)
409
410(MULL x (MOVLconst [c])) => (MULLconst [c] x)
411(ANDL x (MOVLconst [c])) => (ANDLconst [c] x)
412
413(ANDLconst [c] (ANDLconst [d] x)) => (ANDLconst [c & d] x)
414(XORLconst [c] (XORLconst [d] x)) => (XORLconst [c ^ d] x)
415(MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
416
417(ORL x (MOVLconst [c])) => (ORLconst [c] x)
418(XORL x (MOVLconst [c])) => (XORLconst [c] x)
419
420(SHLL x (MOVLconst [c])) => (SHLLconst [c&31] x)
421(SHRL x (MOVLconst [c])) => (SHRLconst [c&31] x)
422(SHRW x (MOVLconst [c])) && c&31 < 16 => (SHRWconst [int16(c&31)] x)
423(SHRW _ (MOVLconst [c])) && c&31 >= 16 => (MOVLconst [0])
424(SHRB x (MOVLconst [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
425(SHRB _ (MOVLconst [c])) && c&31 >= 8 => (MOVLconst [0])
426
427(SARL x (MOVLconst [c])) => (SARLconst [c&31] x)
428(SARW x (MOVLconst [c])) => (SARWconst [int16(min(int64(c&31),15))] x)
429(SARB x (MOVLconst [c])) => (SARBconst [int8(min(int64(c&31),7))] x)
430
431(SARL x (ANDLconst [31] y)) => (SARL x y)
432(SHLL x (ANDLconst [31] y)) => (SHLL x y)
433(SHRL x (ANDLconst [31] y)) => (SHRL x y)
434
435// Constant shift simplifications
436
437(SHLLconst x [0]) => x
438(SHRLconst x [0]) => x
439(SARLconst x [0]) => x
440
441(SHRWconst x [0]) => x
442(SARWconst x [0]) => x
443
444(SHRBconst x [0]) => x
445(SARBconst x [0]) => x
446
447(ROLLconst [0] x) => x
448(ROLWconst [0] x) => x
449(ROLBconst [0] x) => x
450
451// Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
452// because the x86 instructions are defined to use all 5 bits of the shift even
453// for the small shifts. I don't think we'll ever generate a weird shift (e.g.
454// (SHRW x (MOVLconst [24])), but just in case.
455
456(CMPL x (MOVLconst [c])) => (CMPLconst x [c])
457(CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
458(CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
459(CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
460(CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
461(CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))
462
463// Canonicalize the order of arguments to comparisons - helps with CSE.
464(CMP(L|W|B) x y) && canonLessThan(x,y) => (InvertFlags (CMP(L|W|B) y x))
465
466// strength reduction
467// Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf:
468// 1 - addl, shll, leal, negl, subl
469// 3 - imull
470// This limits the rewrites to two instructions.
471// Note that negl always operates in-place,
472// which can require a register-register move
473// to preserve the original value,
474// so it must be used with care.
475(MULLconst [-9] x) => (NEGL (LEAL8 <v.Type> x x))
476(MULLconst [-5] x) => (NEGL (LEAL4 <v.Type> x x))
477(MULLconst [-3] x) => (NEGL (LEAL2 <v.Type> x x))
478(MULLconst [-1] x) => (NEGL x)
479(MULLconst [0] _) => (MOVLconst [0])
480(MULLconst [1] x) => x
481(MULLconst [3] x) => (LEAL2 x x)
482(MULLconst [5] x) => (LEAL4 x x)
483(MULLconst [7] x) => (LEAL2 x (LEAL2 <v.Type> x x))
484(MULLconst [9] x) => (LEAL8 x x)
485(MULLconst [11] x) => (LEAL2 x (LEAL4 <v.Type> x x))
486(MULLconst [13] x) => (LEAL4 x (LEAL2 <v.Type> x x))
487(MULLconst [19] x) => (LEAL2 x (LEAL8 <v.Type> x x))
488(MULLconst [21] x) => (LEAL4 x (LEAL4 <v.Type> x x))
489(MULLconst [25] x) => (LEAL8 x (LEAL2 <v.Type> x x))
490(MULLconst [27] x) => (LEAL8 (LEAL2 <v.Type> x x) (LEAL2 <v.Type> x x))
491(MULLconst [37] x) => (LEAL4 x (LEAL8 <v.Type> x x))
492(MULLconst [41] x) => (LEAL8 x (LEAL4 <v.Type> x x))
493(MULLconst [45] x) => (LEAL8 (LEAL4 <v.Type> x x) (LEAL4 <v.Type> x x))
494(MULLconst [73] x) => (LEAL8 x (LEAL8 <v.Type> x x))
495(MULLconst [81] x) => (LEAL8 (LEAL8 <v.Type> x x) (LEAL8 <v.Type> x x))
496
497(MULLconst [c] x) && isPowerOfTwo(c+1) && c >= 15 => (SUBL (SHLLconst <v.Type> [int32(log32(c+1))] x) x)
498(MULLconst [c] x) && isPowerOfTwo(c-1) && c >= 17 => (LEAL1 (SHLLconst <v.Type> [int32(log32(c-1))] x) x)
499(MULLconst [c] x) && isPowerOfTwo(c-2) && c >= 34 => (LEAL2 (SHLLconst <v.Type> [int32(log32(c-2))] x) x)
500(MULLconst [c] x) && isPowerOfTwo(c-4) && c >= 68 => (LEAL4 (SHLLconst <v.Type> [int32(log32(c-4))] x) x)
501(MULLconst [c] x) && isPowerOfTwo(c-8) && c >= 136 => (LEAL8 (SHLLconst <v.Type> [int32(log32(c-8))] x) x)
502(MULLconst [c] x) && c%3 == 0 && isPowerOfTwo(c/3) => (SHLLconst [int32(log32(c/3))] (LEAL2 <v.Type> x x))
503(MULLconst [c] x) && c%5 == 0 && isPowerOfTwo(c/5) => (SHLLconst [int32(log32(c/5))] (LEAL4 <v.Type> x x))
504(MULLconst [c] x) && c%9 == 0 && isPowerOfTwo(c/9) => (SHLLconst [int32(log32(c/9))] (LEAL8 <v.Type> x x))
505
506// combine add/shift into LEAL
507(ADDL x (SHLLconst [3] y)) => (LEAL8 x y)
508(ADDL x (SHLLconst [2] y)) => (LEAL4 x y)
509(ADDL x (SHLLconst [1] y)) => (LEAL2 x y)
510(ADDL x (ADDL y y)) => (LEAL2 x y)
511(ADDL x (ADDL x y)) => (LEAL2 y x)
512
513// combine ADDL/ADDLconst into LEAL1
514(ADDLconst [c] (ADDL x y)) => (LEAL1 [c] x y)
515(ADDL (ADDLconst [c] x) y) => (LEAL1 [c] x y)
516
517// fold ADDL into LEAL
518(ADDLconst [c] (LEAL [d] {s} x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x)
519(LEAL [c] {s} (ADDLconst [d] x)) && is32Bit(int64(c)+int64(d)) => (LEAL [c+d] {s} x)
520(ADDLconst [c] x:(SP)) => (LEAL [c] x) // so it is rematerializeable
521(LEAL [c] {s} (ADDL x y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y)
522(ADDL x (LEAL [c] {s} y)) && x.Op != OpSB && y.Op != OpSB => (LEAL1 [c] {s} x y)
523
524// fold ADDLconst into LEALx
525(ADDLconst [c] (LEAL1 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL1 [c+d] {s} x y)
526(ADDLconst [c] (LEAL2 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL2 [c+d] {s} x y)
527(ADDLconst [c] (LEAL4 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL4 [c+d] {s} x y)
528(ADDLconst [c] (LEAL8 [d] {s} x y)) && is32Bit(int64(c)+int64(d)) => (LEAL8 [c+d] {s} x y)
529(LEAL1 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL1 [c+d] {s} x y)
530(LEAL2 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL2 [c+d] {s} x y)
531(LEAL2 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+2*int64(d)) && y.Op != OpSB => (LEAL2 [c+2*d] {s} x y)
532(LEAL4 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL4 [c+d] {s} x y)
533(LEAL4 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+4*int64(d)) && y.Op != OpSB => (LEAL4 [c+4*d] {s} x y)
534(LEAL8 [c] {s} (ADDLconst [d] x) y) && is32Bit(int64(c)+int64(d)) && x.Op != OpSB => (LEAL8 [c+d] {s} x y)
535(LEAL8 [c] {s} x (ADDLconst [d] y)) && is32Bit(int64(c)+8*int64(d)) && y.Op != OpSB => (LEAL8 [c+8*d] {s} x y)
536
537// fold shifts into LEALx
538(LEAL1 [c] {s} x (SHLLconst [1] y)) => (LEAL2 [c] {s} x y)
539(LEAL1 [c] {s} x (SHLLconst [2] y)) => (LEAL4 [c] {s} x y)
540(LEAL1 [c] {s} x (SHLLconst [3] y)) => (LEAL8 [c] {s} x y)
541(LEAL2 [c] {s} x (SHLLconst [1] y)) => (LEAL4 [c] {s} x y)
542(LEAL2 [c] {s} x (SHLLconst [2] y)) => (LEAL8 [c] {s} x y)
543(LEAL4 [c] {s} x (SHLLconst [1] y)) => (LEAL8 [c] {s} x y)
544
545// reverse ordering of compare instruction
546(SETL (InvertFlags x)) => (SETG x)
547(SETG (InvertFlags x)) => (SETL x)
548(SETB (InvertFlags x)) => (SETA x)
549(SETA (InvertFlags x)) => (SETB x)
550(SETLE (InvertFlags x)) => (SETGE x)
551(SETGE (InvertFlags x)) => (SETLE x)
552(SETBE (InvertFlags x)) => (SETAE x)
553(SETAE (InvertFlags x)) => (SETBE x)
554(SETEQ (InvertFlags x)) => (SETEQ x)
555(SETNE (InvertFlags x)) => (SETNE x)
556
557// sign extended loads
558// Note: The combined instruction must end up in the same block
559// as the original load. If not, we end up making a value with
560// memory type live in two different blocks, which can lead to
561// multiple memory values alive simultaneously.
562// Make sure we don't combine these ops if the load has another use.
563// This prevents a single load from being split into multiple loads
564// which then might return different values. See test/atomicload.go.
565(MOVBLSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBLSXload <v.Type> [off] {sym} ptr mem)
566(MOVBLZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
567(MOVWLSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWLSXload <v.Type> [off] {sym} ptr mem)
568(MOVWLZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
569
570// replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
571(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLZX x)
572(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLZX x)
573(MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
574(MOVBLSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBLSX x)
575(MOVWLSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVWLSX x)
576
577// Fold extensions and ANDs together.
578(MOVBLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
579(MOVWLZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
580(MOVBLSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
581(MOVWLSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
582
583// Don't extend before storing
584(MOVWstore [off] {sym} ptr (MOVWL(S|Z)X x) mem) => (MOVWstore [off] {sym} ptr x mem)
585(MOVBstore [off] {sym} ptr (MOVBL(S|Z)X x) mem) => (MOVBstore [off] {sym} ptr x mem)
586
587// fold constants into memory operations
588// Note that this is not always a good idea because if not all the uses of
589// the ADDLconst get eliminated, we still have to compute the ADDLconst and we now
590// have potentially two live values (ptr and (ADDLconst [off] ptr)) instead of one.
591// Nevertheless, let's do it!
592(MOV(L|W|B|SS|SD)load [off1] {sym} (ADDLconst [off2] ptr) mem) && is32Bit(int64(off1)+int64(off2)) =>
593 (MOV(L|W|B|SS|SD)load [off1+off2] {sym} ptr mem)
594(MOV(L|W|B|SS|SD)store [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(int64(off1)+int64(off2)) =>
595 (MOV(L|W|B|SS|SD)store [off1+off2] {sym} ptr val mem)
596
597((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
598 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
599((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
600 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
601((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(int64(off1)+int64(off2)) =>
602 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
603((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDLconst [off2] base) val mem) && is32Bit(int64(off1)+int64(off2)) =>
604 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
605((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem) && valoff1.canAdd32(off2) =>
606 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {sym} base mem)
607
608// Fold constants into stores.
609(MOVLstore [off] {sym} ptr (MOVLconst [c]) mem) =>
610 (MOVLstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
611(MOVWstore [off] {sym} ptr (MOVLconst [c]) mem) =>
612 (MOVWstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
613(MOVBstore [off] {sym} ptr (MOVLconst [c]) mem) =>
614 (MOVBstoreconst [makeValAndOff(c,off)] {sym} ptr mem)
615
616// Fold address offsets into constant stores.
617(MOV(L|W|B)storeconst [sc] {s} (ADDLconst [off] ptr) mem) && sc.canAdd32(off) =>
618 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {s} ptr mem)
619
620// We need to fold LEAL into the MOVx ops so that the live variable analysis knows
621// what variables are being read/written by the ops.
622// Note: we turn off this merging for operations on globals when building
623// position-independent code (when Flag_shared is set).
624// PIC needs a spare register to load the PC into. Having the LEAL be
625// a separate instruction gives us that register. Having the LEAL be
626// a separate instruction also allows it to be CSEd (which is good because
627// it compiles to a thunk call).
628(MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1] {sym1} (LEAL [off2] {sym2} base) mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
629 && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
630 (MOV(L|W|B|SS|SD|BLSX|WLSX)load [off1+off2] {mergeSym(sym1,sym2)} base mem)
631
632(MOV(L|W|B|SS|SD)store [off1] {sym1} (LEAL [off2] {sym2} base) val mem) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2)
633 && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
634 (MOV(L|W|B|SS|SD)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
635
636(MOV(L|W|B)storeconst [sc] {sym1} (LEAL [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && sc.canAdd32(off)
637 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
638 (MOV(L|W|B)storeconst [sc.addOffset32(off)] {mergeSym(sym1, sym2)} ptr mem)
639
640((ADD|SUB|MUL|AND|OR|XOR)Lload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
641 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
642 ((ADD|SUB|MUL|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
643((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
644 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
645 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
646((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
647 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
648 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
649((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
650 && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
651 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
652((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
653 && valoff1.canAdd32(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) =>
654 ((ADD|AND|OR|XOR)Lconstmodify [valoff1.addOffset32(off2)] {mergeSym(sym1,sym2)} base mem)
655
656// Merge load/store to op
657((ADD|AND|OR|XOR|SUB|MUL)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|AND|OR|XOR|SUB|MUL)Lload x [off] {sym} ptr mem)
658((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
659((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoadClobber(v, l, x) && clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
660(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
661(MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
662 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
663(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr mem)) mem)
664 && y.Uses==1 && l.Uses==1 && clobber(y, l) =>
665 ((ADD|AND|OR|XOR)Lconstmodify [makeValAndOff(c,off)] {sym} ptr mem)
666
667// fold LEALs together
668(LEAL [off1] {sym1} (LEAL [off2] {sym2} x)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
669 (LEAL [off1+off2] {mergeSym(sym1,sym2)} x)
670
671// LEAL into LEAL1
672(LEAL1 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
673 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
674
675// LEAL1 into LEAL
676(LEAL [off1] {sym1} (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
677 (LEAL1 [off1+off2] {mergeSym(sym1,sym2)} x y)
678
679// LEAL into LEAL[248]
680(LEAL2 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
681 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
682(LEAL4 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
683 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
684(LEAL8 [off1] {sym1} (LEAL [off2] {sym2} x) y) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) && x.Op != OpSB =>
685 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
686
687// LEAL[248] into LEAL
688(LEAL [off1] {sym1} (LEAL2 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
689 (LEAL2 [off1+off2] {mergeSym(sym1,sym2)} x y)
690(LEAL [off1] {sym1} (LEAL4 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
691 (LEAL4 [off1+off2] {mergeSym(sym1,sym2)} x y)
692(LEAL [off1] {sym1} (LEAL8 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
693 (LEAL8 [off1+off2] {mergeSym(sym1,sym2)} x y)
694
695// LEAL[1248] into LEAL[1248]. Only some such merges are possible.
696(LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} y y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
697 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} x y)
698(LEAL1 [off1] {sym1} x (LEAL1 [off2] {sym2} x y)) && is32Bit(int64(off1)+int64(off2)) && canMergeSym(sym1, sym2) =>
699 (LEAL2 [off1+off2] {mergeSym(sym1, sym2)} y x)
700(LEAL2 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+2*int64(off2)) =>
701 (LEAL4 [off1+2*off2] {sym} x y)
702(LEAL4 [off1] {sym} x (LEAL1 [off2] {nil} y y)) && is32Bit(int64(off1)+4*int64(off2)) =>
703 (LEAL8 [off1+4*off2] {sym} x y)
704
705// Absorb InvertFlags into branches.
706(LT (InvertFlags cmp) yes no) => (GT cmp yes no)
707(GT (InvertFlags cmp) yes no) => (LT cmp yes no)
708(LE (InvertFlags cmp) yes no) => (GE cmp yes no)
709(GE (InvertFlags cmp) yes no) => (LE cmp yes no)
710(ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
711(UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
712(ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
713(UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
714(EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
715(NE (InvertFlags cmp) yes no) => (NE cmp yes no)
716
717// Constant comparisons.
718(CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
719(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
720(CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
721(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
722(CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
723
724(CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
725(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
726(CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
727(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
728(CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
729
730(CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
731(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
732(CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
733(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
734(CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)
735
736// Other known comparisons.
737(CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
738(CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
739(CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
740(CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT)
741// TODO: DIVxU also.
742
743// Absorb flag constants into SBB ops.
744(SBBLcarrymask (FlagEQ)) => (MOVLconst [0])
745(SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
746(SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
747(SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
748(SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])
749
750// Absorb flag constants into branches.
751(EQ (FlagEQ) yes no) => (First yes no)
752(EQ (FlagLT_ULT) yes no) => (First no yes)
753(EQ (FlagLT_UGT) yes no) => (First no yes)
754(EQ (FlagGT_ULT) yes no) => (First no yes)
755(EQ (FlagGT_UGT) yes no) => (First no yes)
756
757(NE (FlagEQ) yes no) => (First no yes)
758(NE (FlagLT_ULT) yes no) => (First yes no)
759(NE (FlagLT_UGT) yes no) => (First yes no)
760(NE (FlagGT_ULT) yes no) => (First yes no)
761(NE (FlagGT_UGT) yes no) => (First yes no)
762
763(LT (FlagEQ) yes no) => (First no yes)
764(LT (FlagLT_ULT) yes no) => (First yes no)
765(LT (FlagLT_UGT) yes no) => (First yes no)
766(LT (FlagGT_ULT) yes no) => (First no yes)
767(LT (FlagGT_UGT) yes no) => (First no yes)
768
769(LE (FlagEQ) yes no) => (First yes no)
770(LE (FlagLT_ULT) yes no) => (First yes no)
771(LE (FlagLT_UGT) yes no) => (First yes no)
772(LE (FlagGT_ULT) yes no) => (First no yes)
773(LE (FlagGT_UGT) yes no) => (First no yes)
774
775(GT (FlagEQ) yes no) => (First no yes)
776(GT (FlagLT_ULT) yes no) => (First no yes)
777(GT (FlagLT_UGT) yes no) => (First no yes)
778(GT (FlagGT_ULT) yes no) => (First yes no)
779(GT (FlagGT_UGT) yes no) => (First yes no)
780
781(GE (FlagEQ) yes no) => (First yes no)
782(GE (FlagLT_ULT) yes no) => (First no yes)
783(GE (FlagLT_UGT) yes no) => (First no yes)
784(GE (FlagGT_ULT) yes no) => (First yes no)
785(GE (FlagGT_UGT) yes no) => (First yes no)
786
787(ULT (FlagEQ) yes no) => (First no yes)
788(ULT (FlagLT_ULT) yes no) => (First yes no)
789(ULT (FlagLT_UGT) yes no) => (First no yes)
790(ULT (FlagGT_ULT) yes no) => (First yes no)
791(ULT (FlagGT_UGT) yes no) => (First no yes)
792
793(ULE (FlagEQ) yes no) => (First yes no)
794(ULE (FlagLT_ULT) yes no) => (First yes no)
795(ULE (FlagLT_UGT) yes no) => (First no yes)
796(ULE (FlagGT_ULT) yes no) => (First yes no)
797(ULE (FlagGT_UGT) yes no) => (First no yes)
798
799(UGT (FlagEQ) yes no) => (First no yes)
800(UGT (FlagLT_ULT) yes no) => (First no yes)
801(UGT (FlagLT_UGT) yes no) => (First yes no)
802(UGT (FlagGT_ULT) yes no) => (First no yes)
803(UGT (FlagGT_UGT) yes no) => (First yes no)
804
805(UGE (FlagEQ) yes no) => (First yes no)
806(UGE (FlagLT_ULT) yes no) => (First no yes)
807(UGE (FlagLT_UGT) yes no) => (First yes no)
808(UGE (FlagGT_ULT) yes no) => (First no yes)
809(UGE (FlagGT_UGT) yes no) => (First yes no)
810
811// Absorb flag constants into SETxx ops.
812(SETEQ (FlagEQ)) => (MOVLconst [1])
813(SETEQ (FlagLT_ULT)) => (MOVLconst [0])
814(SETEQ (FlagLT_UGT)) => (MOVLconst [0])
815(SETEQ (FlagGT_ULT)) => (MOVLconst [0])
816(SETEQ (FlagGT_UGT)) => (MOVLconst [0])
817
818(SETNE (FlagEQ)) => (MOVLconst [0])
819(SETNE (FlagLT_ULT)) => (MOVLconst [1])
820(SETNE (FlagLT_UGT)) => (MOVLconst [1])
821(SETNE (FlagGT_ULT)) => (MOVLconst [1])
822(SETNE (FlagGT_UGT)) => (MOVLconst [1])
823
824(SETL (FlagEQ)) => (MOVLconst [0])
825(SETL (FlagLT_ULT)) => (MOVLconst [1])
826(SETL (FlagLT_UGT)) => (MOVLconst [1])
827(SETL (FlagGT_ULT)) => (MOVLconst [0])
828(SETL (FlagGT_UGT)) => (MOVLconst [0])
829
830(SETLE (FlagEQ)) => (MOVLconst [1])
831(SETLE (FlagLT_ULT)) => (MOVLconst [1])
832(SETLE (FlagLT_UGT)) => (MOVLconst [1])
833(SETLE (FlagGT_ULT)) => (MOVLconst [0])
834(SETLE (FlagGT_UGT)) => (MOVLconst [0])
835
836(SETG (FlagEQ)) => (MOVLconst [0])
837(SETG (FlagLT_ULT)) => (MOVLconst [0])
838(SETG (FlagLT_UGT)) => (MOVLconst [0])
839(SETG (FlagGT_ULT)) => (MOVLconst [1])
840(SETG (FlagGT_UGT)) => (MOVLconst [1])
841
842(SETGE (FlagEQ)) => (MOVLconst [1])
843(SETGE (FlagLT_ULT)) => (MOVLconst [0])
844(SETGE (FlagLT_UGT)) => (MOVLconst [0])
845(SETGE (FlagGT_ULT)) => (MOVLconst [1])
846(SETGE (FlagGT_UGT)) => (MOVLconst [1])
847
848(SETB (FlagEQ)) => (MOVLconst [0])
849(SETB (FlagLT_ULT)) => (MOVLconst [1])
850(SETB (FlagLT_UGT)) => (MOVLconst [0])
851(SETB (FlagGT_ULT)) => (MOVLconst [1])
852(SETB (FlagGT_UGT)) => (MOVLconst [0])
853
854(SETBE (FlagEQ)) => (MOVLconst [1])
855(SETBE (FlagLT_ULT)) => (MOVLconst [1])
856(SETBE (FlagLT_UGT)) => (MOVLconst [0])
857(SETBE (FlagGT_ULT)) => (MOVLconst [1])
858(SETBE (FlagGT_UGT)) => (MOVLconst [0])
859
860(SETA (FlagEQ)) => (MOVLconst [0])
861(SETA (FlagLT_ULT)) => (MOVLconst [0])
862(SETA (FlagLT_UGT)) => (MOVLconst [1])
863(SETA (FlagGT_ULT)) => (MOVLconst [0])
864(SETA (FlagGT_UGT)) => (MOVLconst [1])
865
866(SETAE (FlagEQ)) => (MOVLconst [1])
867(SETAE (FlagLT_ULT)) => (MOVLconst [0])
868(SETAE (FlagLT_UGT)) => (MOVLconst [1])
869(SETAE (FlagGT_ULT)) => (MOVLconst [0])
870(SETAE (FlagGT_UGT)) => (MOVLconst [1])
871
872// Remove redundant *const ops
873(ADDLconst [c] x) && c==0 => x
874(SUBLconst [c] x) && c==0 => x
875(ANDLconst [c] _) && c==0 => (MOVLconst [0])
876(ANDLconst [c] x) && c==-1 => x
877(ORLconst [c] x) && c==0 => x
878(ORLconst [c] _) && c==-1 => (MOVLconst [-1])
879(XORLconst [c] x) && c==0 => x
880// TODO: since we got rid of the W/B versions, we might miss
881// things like (ANDLconst [0x100] x) which were formerly
882// (ANDBconst [0] x). Probably doesn't happen very often.
883// If we cared, we might do:
884// (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 => (MOVLconst [0])
885
886// Convert constant subtracts to constant adds
887(SUBLconst [c] x) => (ADDLconst [-c] x)
888
889// generic constant folding
890// TODO: more of this
891(ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
892(ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
893(SARLconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
894(SARWconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
895(SARBconst [c] (MOVLconst [d])) => (MOVLconst [d>>uint64(c)])
896(NEGL (MOVLconst [c])) => (MOVLconst [-c])
897(MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
898(ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
899(ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
900(XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
901(NOTL (MOVLconst [c])) => (MOVLconst [^c])
902
903// generic simplifications
904// TODO: more of this
905(ADDL x (NEGL y)) => (SUBL x y)
906(SUBL x x) => (MOVLconst [0])
907(ANDL x x) => x
908(ORL x x) => x
909(XORL x x) => (MOVLconst [0])
910
911// checking AND against 0.
912(CMP(L|W|B)const l:(ANDL x y) [0]) && l.Uses==1 => (TEST(L|W|B) x y)
913(CMPLconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTLconst [c] x)
914(CMPWconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTWconst [int16(c)] x)
915(CMPBconst l:(ANDLconst [c] x) [0]) && l.Uses==1 => (TESTBconst [int8(c)] x)
916
917// TEST %reg,%reg is shorter than CMP
918(CMP(L|W|B)const x [0]) => (TEST(L|W|B) x x)
919
920// Convert LEAL1 back to ADDL if we can
921(LEAL1 [0] {nil} x y) => (ADDL x y)
922
923// For PIC, break floating-point constant loading into two instructions so we have
924// a register to use for holding the address of the constant pool entry.
925(MOVSSconst [c]) && config.ctxt.Flag_shared => (MOVSSconst2 (MOVSSconst1 [c]))
926(MOVSDconst [c]) && config.ctxt.Flag_shared => (MOVSDconst2 (MOVSDconst1 [c]))
927
928(CMP(L|W|B) l:(MOV(L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l) && clobber(l) => (CMP(L|W|B)load {sym} [off] ptr x mem)
929(CMP(L|W|B) x l:(MOV(L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l) && clobber(l) => (InvertFlags (CMP(L|W|B)load {sym} [off] ptr x mem))
930
931(CMP(L|W|B)const l:(MOV(L|W|B)load {sym} [off] ptr mem) [c])
932 && l.Uses == 1
933 && clobber(l) =>
934 @l.Block (CMP(L|W|B)constload {sym} [makeValAndOff(int32(c),off)] ptr mem)
935
936(CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
937(CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [makeValAndOff(int32(int16(c)),off)] ptr mem)
938(CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [makeValAndOff(int32(int8(c)),off)] ptr mem)
939
940(MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read8(sym, int64(off)))])
941(MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
942(MOVLload [off] {sym} (SB) _) && symIsRO(sym) => (MOVLconst [int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
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