1// Copyright 2022 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5(Add(Ptr|64|32|16|8) ...) => (ADDV ...)
6(Add(32|64)F ...) => (ADD(F|D) ...)
7
8(Sub(Ptr|64|32|16|8) ...) => (SUBV ...)
9(Sub(32|64)F ...) => (SUB(F|D) ...)
10
11(Mul(64|32|16|8) ...) => (MULV ...)
12(Mul(32|64)F ...) => (MUL(F|D) ...)
13(Select0 (Mul64uhilo x y)) => (MULHVU x y)
14(Select1 (Mul64uhilo x y)) => (MULV x y)
15(Select0 (Mul64uover x y)) => (MULV x y)
16(Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (MULHVU x y) (MOVVconst <typ.UInt64> [0]))
17
18// 32 mul 32 -> 64
19(MULV r:(MOVWUreg x) s:(MOVWUreg y)) && r.Uses == 1 && s.Uses == 1 => (MULWVWU x y)
20(MULV r:(MOVWreg x) s:(MOVWreg y)) && r.Uses == 1 && s.Uses == 1 => (MULWVW x y)
21
22(Hmul64 ...) => (MULHV ...)
23(Hmul64u ...) => (MULHVU ...)
24(Hmul32 ...) => (MULH ...)
25(Hmul32u ...) => (MULHU ...)
26
27(Div64 x y) => (DIVV x y)
28(Div64u ...) => (DIVVU ...)
29(Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y))
30(Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))
31(Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y))
32(Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))
33(Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y))
34(Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))
35(Div(32|64)F ...) => (DIV(F|D) ...)
36
37(Mod64 x y) => (REMV x y)
38(Mod64u ...) => (REMVU ...)
39(Mod32 x y) => (REMV (SignExt32to64 x) (SignExt32to64 y))
40(Mod32u x y) => (REMVU (ZeroExt32to64 x) (ZeroExt32to64 y))
41(Mod16 x y) => (REMV (SignExt16to64 x) (SignExt16to64 y))
42(Mod16u x y) => (REMVU (ZeroExt16to64 x) (ZeroExt16to64 y))
43(Mod8 x y) => (REMV (SignExt8to64 x) (SignExt8to64 y))
44(Mod8u x y) => (REMVU (ZeroExt8to64 x) (ZeroExt8to64 y))
45
46(Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
47(Select1 <t> (Add64carry x y c)) =>
48 (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
49
50(Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
51(Select1 <t> (Sub64borrow x y c)) =>
52 (OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
53
54// (x + y) / 2 with x>=y => (x - y) / 2 + y
55(Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
56
57(And(64|32|16|8) ...) => (AND ...)
58(Or(64|32|16|8) ...) => (OR ...)
59(Xor(64|32|16|8) ...) => (XOR ...)
60
61// shifts
62// hardware instruction uses only the low 6 bits of the shift
63// we compare to 64 to ensure Go semantics for large shifts
64
65// left shift
66(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLLV x y)
67(Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLL x y)
68(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLLV x y)
69(Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLLV x y)
70
71(Lsh64x64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
72(Lsh64x32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
73(Lsh64x16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
74(Lsh64x8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
75
76(Lsh32x64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLL <t> x y) (SGTU (MOVVconst <typ.UInt64> [32]) y))
77(Lsh32x32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLL <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt32to64 y)))
78(Lsh32x16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLL <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt16to64 y)))
79(Lsh32x8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLL <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt8to64 y)))
80
81(Lsh16x64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
82(Lsh16x32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
83(Lsh16x16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
84(Lsh16x8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
85
86(Lsh8x64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
87(Lsh8x32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
88(Lsh8x16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
89(Lsh8x8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SLLV <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
90
91// unsigned right shift
92(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRLV x y)
93(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRL x y)
94(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRLV (ZeroExt16to64 x) y)
95(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRLV (ZeroExt8to64 x) y)
96
97(Rsh64Ux64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> x y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
98(Rsh64Ux32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
99(Rsh64Ux16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
100(Rsh64Ux8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
101
102(Rsh32Ux64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRL <t> x y) (SGTU (MOVVconst <typ.UInt64> [32]) y))
103(Rsh32Ux32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRL <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt32to64 y)))
104(Rsh32Ux16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRL <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt16to64 y)))
105(Rsh32Ux8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRL <t> x (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [32]) (ZeroExt8to64 y)))
106
107(Rsh16Ux64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt16to64 x) y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
108(Rsh16Ux32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
109(Rsh16Ux16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
110(Rsh16Ux8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
111
112(Rsh8Ux64 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt8to64 x) y) (SGTU (MOVVconst <typ.UInt64> [64]) y))
113(Rsh8Ux32 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
114(Rsh8Ux16 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
115(Rsh8Ux8 <t> x y) && !shiftIsBounded(v) => (MASKEQZ (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y)))
116
117// signed right shift
118(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAV x y)
119(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRA x y)
120(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAV (SignExt16to64 x) y)
121(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAV (SignExt8to64 x) y)
122
123(Rsh64x64 <t> x y) && !shiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
124(Rsh64x32 <t> x y) && !shiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
125(Rsh64x16 <t> x y) && !shiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
126(Rsh64x8 <t> x y) && !shiftIsBounded(v) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
127
128(Rsh32x64 <t> x y) && !shiftIsBounded(v) => (SRA x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [31]))) y))
129(Rsh32x32 <t> x y) && !shiftIsBounded(v) => (SRA x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [31]))) (ZeroExt32to64 y)))
130(Rsh32x16 <t> x y) && !shiftIsBounded(v) => (SRA x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [31]))) (ZeroExt16to64 y)))
131(Rsh32x8 <t> x y) && !shiftIsBounded(v) => (SRA x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [31]))) (ZeroExt8to64 y)))
132
133(Rsh16x64 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
134(Rsh16x32 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
135(Rsh16x16 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
136(Rsh16x8 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
137
138(Rsh8x64 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
139(Rsh8x32 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
140(Rsh8x16 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
141(Rsh8x8 <t> x y) && !shiftIsBounded(v) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
142
143
144// revb2h
145// ((x>>8) | (x<<8)) => (REVB2H x), the type of x is uint16
146((OR|XOR|ADDV) <typ.UInt16> (SRLVconst [8] <typ.UInt16> x) (SLLVconst [8] <typ.UInt16> x)) => (REVB2H x)
147
148// ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), the type of x is uint32
149((OR|XOR|ADDV) (SRLconst [8] (ANDconst [c1] x)) (SLLconst [8] (ANDconst [c2] x)))
150 && uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff
151 => (REVB2H x)
152
153// revb4h
154// ((x & 0xff00ff00ff00ff00)>>8) | ((x & 0x00ff00ff00ff00ff)<<8), the type of x is uint64
155((OR|XOR|ADDV) (SRLVconst [8] (AND (MOVVconst [c1]) x)) (SLLVconst [8] (AND (MOVVconst [c2]) x)))
156 && uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff
157 => (REVB4H x)
158
159// ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), the type of x is uint64
160((OR|XOR|ADDV) (SRLVconst [8] (AND (MOVVconst [c1]) x)) (SLLVconst [8] (ANDconst [c2] x)))
161 && uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff
162 => (REVB4H (ANDconst <x.Type> [0xffffffff] x))
163
164// bitfield ops
165
166// bstrpickv
167// (x << lc) >> rc
168(SRLVconst [rc] (SLLVconst [lc] x)) && lc <= rc => (BSTRPICKV [rc-lc + ((64-lc)-1)<<6] x)
169// uint64(x) >> rc
170(SRLVconst [rc] (MOVWUreg x)) && rc < 32 => (BSTRPICKV [rc + 31<<6] x)
171(SRLVconst [rc] (MOVHUreg x)) && rc < 16 => (BSTRPICKV [rc + 15<<6] x)
172(SRLVconst [rc] (MOVBUreg x)) && rc < 8 => (BSTRPICKV [rc + 7<<6] x)
173// uint64(x >> rc)
174(MOVWUreg (SRLVconst [rc] x)) && rc < 32 => (BSTRPICKV [rc + (31+rc)<<6] x)
175(MOVHUreg (SRLVconst [rc] x)) && rc < 16 => (BSTRPICKV [rc + (15+rc)<<6] x)
176(MOVBUreg (SRLVconst [rc] x)) && rc < 8 => (BSTRPICKV [rc + (7+rc)<<6] x)
177
178// rotates
179(RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
180(RotateLeft8 <t> x y) => (OR <t> (SLLV <t> x (ANDconst <typ.Int64> [7] y)) (SRLV <t> (ZeroExt8to64 x) (ANDconst <typ.Int64> [7] (NEGV <typ.Int64> y))))
181(RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
182(RotateLeft16 <t> x y) => (ROTR <t> (OR <typ.UInt32> (ZeroExt16to32 x) (SLLVconst <t> (ZeroExt16to32 x) [16])) (NEGV <typ.Int64> y))
183(RotateLeft32 x y) => (ROTR x (NEGV <y.Type> y))
184(RotateLeft64 x y) => (ROTRV x (NEGV <y.Type> y))
185
186// unary ops
187(Neg(64|32|16|8) ...) => (NEGV ...)
188(Neg(32|64)F ...) => (NEG(F|D) ...)
189
190(Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
191
192(BitLen64 <t> x) => (NEGV <t> (SUBVconst <t> [64] (CLZV <t> x)))
193(BitLen32 <t> x) => (NEGV <t> (SUBVconst <t> [32] (CLZW <t> x)))
194(BitLen(16|8) x) => (BitLen64 (ZeroExt(16|8)to64 x))
195(Bswap(16|32|64) ...) => (REVB(2H|2W|V) ...)
196(BitRev8 ...) => (BITREV4B ...)
197(BitRev16 <t> x) => (REVB2H (BITREV4B <t> x))
198(BitRev32 ...) => (BITREVW ...)
199(BitRev64 ...) => (BITREVV ...)
200(Ctz(64|32|16|8)NonZero ...) => (Ctz64 ...)
201(Ctz(32|64) ...) => (CTZ(W|V) ...)
202(Ctz16 x) => (CTZV (OR <typ.UInt64> x (MOVVconst [1<<16])))
203(Ctz8 x) => (CTZV (OR <typ.UInt64> x (MOVVconst [1<<8])))
204
205(PopCount64 <t> x) => (MOVVfpgp <t> (VPCNT64 <typ.Float64> (MOVVgpfp <typ.Float64> x)))
206(PopCount32 <t> x) => (MOVWfpgp <t> (VPCNT32 <typ.Float32> (MOVWgpfp <typ.Float32> x)))
207(PopCount16 <t> x) => (MOVWfpgp <t> (VPCNT16 <typ.Float32> (MOVWgpfp <typ.Float32> (ZeroExt16to32 x))))
208
209// math package intrinsics
210(Sqrt ...) => (SQRTD ...)
211(Sqrt32 ...) => (SQRTF ...)
212
213(Abs ...) => (ABSD ...)
214(Copysign ...) => (FCOPYSGD ...)
215
216(RoundToEven ...) => (FRINTND ...)
217(Floor ...) => (FRINTMD ...)
218(Ceil ...) => (FRINTPD ...)
219(Trunc ...) => (FRINTZD ...)
220
221(Min(64|32)F ...) => (FMIN(D|F) ...)
222(Max(64|32)F ...) => (FMAX(D|F) ...)
223
224// boolean ops -- booleans are represented with 0=false, 1=true
225(AndB ...) => (AND ...)
226(OrB ...) => (OR ...)
227(EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
228(NeqB ...) => (XOR ...)
229(Not x) => (XORconst [1] x)
230
231// constants
232(Const(64|32|16|8) [val]) => (MOVVconst [int64(val)])
233(Const(32|64)F [val]) => (MOV(F|D)const [float64(val)])
234(ConstNil) => (MOVVconst [0])
235(ConstBool [t]) => (MOVVconst [int64(b2i(t))])
236
237(Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63])
238
239// truncations
240// Because we ignore high parts of registers, truncates are just copies.
241(Trunc16to8 ...) => (Copy ...)
242(Trunc32to8 ...) => (Copy ...)
243(Trunc32to16 ...) => (Copy ...)
244(Trunc64to8 ...) => (Copy ...)
245(Trunc64to16 ...) => (Copy ...)
246(Trunc64to32 ...) => (Copy ...)
247
248// Zero-/Sign-extensions
249(ZeroExt8to16 ...) => (MOVBUreg ...)
250(ZeroExt8to32 ...) => (MOVBUreg ...)
251(ZeroExt16to32 ...) => (MOVHUreg ...)
252(ZeroExt8to64 ...) => (MOVBUreg ...)
253(ZeroExt16to64 ...) => (MOVHUreg ...)
254(ZeroExt32to64 ...) => (MOVWUreg ...)
255
256(SignExt8to16 ...) => (MOVBreg ...)
257(SignExt8to32 ...) => (MOVBreg ...)
258(SignExt16to32 ...) => (MOVHreg ...)
259(SignExt8to64 ...) => (MOVBreg ...)
260(SignExt16to64 ...) => (MOVHreg ...)
261(SignExt32to64 ...) => (MOVWreg ...)
262
263// float <=> int conversion
264(Cvt32to32F ...) => (MOVWF ...)
265(Cvt32to64F ...) => (MOVWD ...)
266(Cvt64to32F ...) => (MOVVF ...)
267(Cvt64to64F ...) => (MOVVD ...)
268(Cvt32Fto32 ...) => (TRUNCFW ...)
269(Cvt64Fto32 ...) => (TRUNCDW ...)
270(Cvt32Fto64 ...) => (TRUNCFV ...)
271(Cvt64Fto64 ...) => (TRUNCDV ...)
272(Cvt32Fto64F ...) => (MOVFD ...)
273(Cvt64Fto32F ...) => (MOVDF ...)
274
275(CvtBoolToUint8 ...) => (Copy ...)
276
277(Round(32|64)F ...) => (LoweredRound(32|64)F ...)
278
279// comparisons
280(Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
281(Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
282(Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
283(Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
284(EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
285(Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
286
287(Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0]))
288(Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0]))
289(Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0]))
290(Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0]))
291(NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0]))
292(Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
293
294(Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x))
295(Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x))
296(Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x))
297(Less64 x y) => (SGT y x)
298(Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
299
300(Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))
301(Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))
302(Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))
303(Less64U x y) => (SGTU y x)
304
305(Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y)))
306(Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y)))
307(Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y)))
308(Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y))
309(Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
310
311(Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)))
312(Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)))
313(Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)))
314(Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y))
315
316(OffPtr [off] ptr:(SP)) => (MOVVaddr [int32(off)] ptr)
317(OffPtr [off] ptr) => (ADDVconst [off] ptr)
318
319(Addr {sym} base) => (MOVVaddr {sym} base)
320(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVVaddr {sym} (SPanchored base mem))
321(LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVVaddr {sym} base)
322
323// loads
324(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
325(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
326(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
327(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
328(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
329(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
330(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
331(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
332(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
333(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
334
335// stores
336(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
337(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
338(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
339(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
340(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
341(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
342
343// zeroing
344(Zero [0] _ mem) => mem
345(Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem)
346(Zero [2] ptr mem) => (MOVHstore ptr (MOVVconst [0]) mem)
347(Zero [3] ptr mem) =>
348 (MOVBstore [2] ptr (MOVVconst [0])
349 (MOVHstore ptr (MOVVconst [0]) mem))
350(Zero [4] {t} ptr mem) => (MOVWstore ptr (MOVVconst [0]) mem)
351(Zero [5] ptr mem) =>
352 (MOVBstore [4] ptr (MOVVconst [0])
353 (MOVWstore ptr (MOVVconst [0]) mem))
354(Zero [6] ptr mem) =>
355 (MOVHstore [4] ptr (MOVVconst [0])
356 (MOVWstore ptr (MOVVconst [0]) mem))
357(Zero [7] ptr mem) =>
358 (MOVWstore [3] ptr (MOVVconst [0])
359 (MOVWstore ptr (MOVVconst [0]) mem))
360(Zero [8] {t} ptr mem) => (MOVVstore ptr (MOVVconst [0]) mem)
361(Zero [9] ptr mem) =>
362 (MOVBstore [8] ptr (MOVVconst [0])
363 (MOVVstore ptr (MOVVconst [0]) mem))
364(Zero [10] ptr mem) =>
365 (MOVHstore [8] ptr (MOVVconst [0])
366 (MOVVstore ptr (MOVVconst [0]) mem))
367(Zero [11] ptr mem) =>
368 (MOVWstore [7] ptr (MOVVconst [0])
369 (MOVVstore ptr (MOVVconst [0]) mem))
370(Zero [12] ptr mem) =>
371 (MOVWstore [8] ptr (MOVVconst [0])
372 (MOVVstore ptr (MOVVconst [0]) mem))
373(Zero [13] ptr mem) =>
374 (MOVVstore [5] ptr (MOVVconst [0])
375 (MOVVstore ptr (MOVVconst [0]) mem))
376(Zero [14] ptr mem) =>
377 (MOVVstore [6] ptr (MOVVconst [0])
378 (MOVVstore ptr (MOVVconst [0]) mem))
379(Zero [15] ptr mem) =>
380 (MOVVstore [7] ptr (MOVVconst [0])
381 (MOVVstore ptr (MOVVconst [0]) mem))
382(Zero [16] ptr mem) =>
383 (MOVVstore [8] ptr (MOVVconst [0])
384 (MOVVstore ptr (MOVVconst [0]) mem))
385
386(Zero [s] ptr mem) && s > 16 && s < 192 => (LoweredZero [s] ptr mem)
387(Zero [s] ptr mem) && s >= 192 => (LoweredZeroLoop [s] ptr mem)
388
389// moves
390(Move [0] _ _ mem) => mem
391(Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem)
392(Move [2] dst src mem) => (MOVHstore dst (MOVHUload src mem) mem)
393(Move [3] dst src mem) =>
394 (MOVBstore [2] dst (MOVBUload [2] src mem)
395 (MOVHstore dst (MOVHUload src mem) mem))
396(Move [4] dst src mem) => (MOVWstore dst (MOVWUload src mem) mem)
397(Move [5] dst src mem) =>
398 (MOVBstore [4] dst (MOVBUload [4] src mem)
399 (MOVWstore dst (MOVWUload src mem) mem))
400(Move [6] dst src mem) =>
401 (MOVHstore [4] dst (MOVHUload [4] src mem)
402 (MOVWstore dst (MOVWUload src mem) mem))
403(Move [7] dst src mem) =>
404 (MOVWstore [3] dst (MOVWUload [3] src mem)
405 (MOVWstore dst (MOVWUload src mem) mem))
406(Move [8] dst src mem) => (MOVVstore dst (MOVVload src mem) mem)
407(Move [9] dst src mem) =>
408 (MOVBstore [8] dst (MOVBUload [8] src mem)
409 (MOVVstore dst (MOVVload src mem) mem))
410(Move [10] dst src mem) =>
411 (MOVHstore [8] dst (MOVHUload [8] src mem)
412 (MOVVstore dst (MOVVload src mem) mem))
413(Move [11] dst src mem) =>
414 (MOVWstore [7] dst (MOVWload [7] src mem)
415 (MOVVstore dst (MOVVload src mem) mem))
416(Move [12] dst src mem) =>
417 (MOVWstore [8] dst (MOVWUload [8] src mem)
418 (MOVVstore dst (MOVVload src mem) mem))
419(Move [13] dst src mem) =>
420 (MOVVstore [5] dst (MOVVload [5] src mem)
421 (MOVVstore dst (MOVVload src mem) mem))
422(Move [14] dst src mem) =>
423 (MOVVstore [6] dst (MOVVload [6] src mem)
424 (MOVVstore dst (MOVVload src mem) mem))
425(Move [15] dst src mem) =>
426 (MOVVstore [7] dst (MOVVload [7] src mem)
427 (MOVVstore dst (MOVVload src mem) mem))
428(Move [16] dst src mem) =>
429 (MOVVstore [8] dst (MOVVload [8] src mem)
430 (MOVVstore dst (MOVVload src mem) mem))
431
432(Move [s] dst src mem) && s > 16 && s < 192 && logLargeCopy(v, s) => (LoweredMove [s] dst src mem)
433(Move [s] dst src mem) && s >= 192 && logLargeCopy(v, s) => (LoweredMoveLoop [s] dst src mem)
434
435// float <=> int register moves, with no conversion.
436// These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}.
437(MOVVload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (MOVVfpgp val)
438(MOVDload [off] {sym} ptr (MOVVstore [off] {sym} ptr val _)) => (MOVVgpfp val)
439(MOVWUload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (ZeroExt32to64 (MOVWfpgp <typ.Float32> val))
440(MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
441
442// If the memory load and store operations use the same ptr, they are combined into a direct move operation between registers.
443(MOV(V|W|H|B)load [off] {sym} ptr (MOV(V|W|H|B)store [off] {sym} ptr x _)) => (MOV(V|W|H|B)reg x)
444(MOV(W|H|B)Uload [off] {sym} ptr (MOV(W|H|B)store [off] {sym} ptr x _)) => (MOV(W|H|B)Ureg x)
445
446// Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
447(MOVVstore [off] {sym} ptr (MOVVfpgp val) mem) => (MOVDstore [off] {sym} ptr val mem)
448(MOVDstore [off] {sym} ptr (MOVVgpfp val) mem) => (MOVVstore [off] {sym} ptr val mem)
449(MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) => (MOVFstore [off] {sym} ptr val mem)
450(MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
451
452// calls
453(StaticCall ...) => (CALLstatic ...)
454(ClosureCall ...) => (CALLclosure ...)
455(InterCall ...) => (CALLinter ...)
456(TailCall ...) => (CALLtail ...)
457(TailCallInter ...) => (CALLtailinter ...)
458
459// atomic intrinsics
460(AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...)
461(AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...)
462
463(AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...)
464(AtomicStore(8|32|64)Variant ...) => (LoweredAtomicStore(8|32|64)Variant ...)
465(AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...)
466
467(AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
468(AtomicExchange8Variant ...) => (LoweredAtomicExchange8Variant ...)
469
470(AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
471
472// Loong64's 32-bit atomic operation instructions ll.w and amcasw are both sign-extended,
473// so the input parameters need to be sign-extended to 64 bits, otherwise the subsequent
474// comparison operations may not produce the expected results.
475//
476(AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem)
477(AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...)
478(AtomicCompareAndSwap32Variant ptr old new mem) => (LoweredAtomicCas32Variant ptr (SignExt32to64 old) new mem)
479(AtomicCompareAndSwap64Variant ...) => (LoweredAtomicCas64Variant ...)
480
481// Atomic memory logical operations (old style).
482//
483// AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3, ^((uint8(val) ^ 0xff) << ((ptr & 3) * 8)))
484// AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3, uint32(val) << ((ptr & 3) * 8))
485//
486(AtomicAnd8 ptr val mem) =>
487 (LoweredAtomicAnd32 (AND <typ.Uintptr> (MOVVconst [^3]) ptr)
488 (NORconst [0] <typ.UInt32> (SLLV <typ.UInt32> (XORconst <typ.UInt32> [0xff] (ZeroExt8to32 val))
489 (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr)))) mem)
490
491(AtomicOr8 ptr val mem) =>
492 (LoweredAtomicOr32 (AND <typ.Uintptr> (MOVVconst [^3]) ptr)
493 (SLLV <typ.UInt32> (ZeroExt8to32 val)
494 (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))) mem)
495
496(AtomicAnd32 ...) => (LoweredAtomicAnd32 ...)
497(AtomicOr32 ...) => (LoweredAtomicOr32 ...)
498
499// Atomic memory logical operations (new style).
500(AtomicAnd(64|32)value ...) => (LoweredAtomicAnd(64|32)value ...)
501(AtomicOr(64|32)value ...) => (LoweredAtomicOr(64|32)value ...)
502
503// checks
504(NilCheck ...) => (LoweredNilCheck ...)
505(IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
506(IsInBounds idx len) => (SGTU len idx)
507(IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
508
509// pseudo-ops
510(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
511(GetCallerSP ...) => (LoweredGetCallerSP ...)
512(GetCallerPC ...) => (LoweredGetCallerPC ...)
513
514(If cond yes no) => (NEZ (MOVBUreg <typ.UInt64> cond) yes no)
515(MOVBUreg x:((SGT|SGTU) _ _)) => x
516(MOVBUreg x:(XOR (MOVVconst [1]) ((SGT|SGTU) _ _))) => x
517
518(JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (MOVVaddr <typ.Uintptr> {makeJumpTableSym(b)} (SB)))
519
520// Write barrier.
521(WB ...) => (LoweredWB ...)
522
523// Publication barrier as intrinsic
524(PubBarrier ...) => (LoweredPubBarrier ...)
525
526(PanicBounds ...) => (LoweredPanicBoundsRR ...)
527(LoweredPanicBoundsRR [kind] x (MOVVconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem)
528(LoweredPanicBoundsRR [kind] (MOVVconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem)
529(LoweredPanicBoundsRC [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem)
530(LoweredPanicBoundsCR [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem)
531
532(CondSelect <t> x y cond) => (OR (MASKEQZ <t> x cond) (MASKNEZ <t> y cond))
533
534// c > d-x => x > d-c
535(SGT (MOVVconst [c]) (NEGV (SUBVconst [d] x))) && is32Bit(d-c) => (SGT x (MOVVconst [d-c]))
536
537(SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x)
538(SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
539
540// fold offset into address
541(ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr)
542
543// fold address into load/store
544// Do not fold global variable access in -dynlink mode, where it will be rewritten
545// to use the GOT via REGTMP, which currently cannot handle large offset.
546(MOV(B|BU|H|HU|W|WU|V|F|D)load [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
547 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
548 (MOV(B|BU|H|HU|W|WU|V|F|D)load [off1+int32(off2)] {sym} ptr mem)
549
550(MOV(B|H|W|V|F|D)store [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
551 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
552 (MOV(B|H|W|V|F|D)store [off1+int32(off2)] {sym} ptr val mem)
553
554(MOV(B|BU|H|HU|W|WU|V|F|D)load [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
555 && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
556 (MOV(B|BU|H|HU|W|WU|V|F|D)load [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
557
558(MOV(B|H|W|V|F|D)store [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2)
559 && is32Bit(int64(off1)+int64(off2)) && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
560 (MOV(B|H|W|V|F|D)store [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
561
562// don't extend after proper load
563(MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
564(MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
565(MOVHreg x:(MOVBload _ _)) => (MOVVreg x)
566(MOVHreg x:(MOVBUload _ _)) => (MOVVreg x)
567(MOVHreg x:(MOVHload _ _)) => (MOVVreg x)
568(MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x)
569(MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x)
570(MOVWreg x:(MOVBload _ _)) => (MOVVreg x)
571(MOVWreg x:(MOVBUload _ _)) => (MOVVreg x)
572(MOVWreg x:(MOVHload _ _)) => (MOVVreg x)
573(MOVWreg x:(MOVHUload _ _)) => (MOVVreg x)
574(MOVWreg x:(MOVWload _ _)) => (MOVVreg x)
575(MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x)
576(MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x)
577(MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x)
578(MOVBreg x:(MOVBloadidx _ _ _)) => (MOVVreg x)
579(MOVBUreg x:(MOVBUloadidx _ _ _)) => (MOVVreg x)
580(MOVHreg x:(MOVBloadidx _ _ _)) => (MOVVreg x)
581(MOVHreg x:(MOVBUloadidx _ _ _)) => (MOVVreg x)
582(MOVHreg x:(MOVHloadidx _ _ _)) => (MOVVreg x)
583(MOVHUreg x:(MOVBUloadidx _ _ _)) => (MOVVreg x)
584(MOVHUreg x:(MOVHUloadidx _ _ _)) => (MOVVreg x)
585(MOVWreg x:(MOVBloadidx _ _ _)) => (MOVVreg x)
586(MOVWreg x:(MOVBUloadidx _ _ _)) => (MOVVreg x)
587(MOVWreg x:(MOVHloadidx _ _ _)) => (MOVVreg x)
588(MOVWreg x:(MOVHUloadidx _ _ _)) => (MOVVreg x)
589(MOVWreg x:(MOVWloadidx _ _ _)) => (MOVVreg x)
590(MOVWUreg x:(MOVBUloadidx _ _ _)) => (MOVVreg x)
591(MOVWUreg x:(MOVHUloadidx _ _ _)) => (MOVVreg x)
592(MOVWUreg x:(MOVWUloadidx _ _ _)) => (MOVVreg x)
593
594// fold double extensions
595(MOVBreg x:(MOVBreg _)) => (MOVVreg x)
596(MOVBUreg x:(MOVBUreg _)) => (MOVVreg x)
597(MOVHreg x:(MOVBreg _)) => (MOVVreg x)
598(MOVHreg x:(MOVBUreg _)) => (MOVVreg x)
599(MOVHreg x:(MOVHreg _)) => (MOVVreg x)
600(MOVHUreg x:(MOVBUreg _)) => (MOVVreg x)
601(MOVHUreg x:(MOVHUreg _)) => (MOVVreg x)
602(MOVWreg x:(MOVBreg _)) => (MOVVreg x)
603(MOVWreg x:(MOVBUreg _)) => (MOVVreg x)
604(MOVWreg x:(MOVHreg _)) => (MOVVreg x)
605(MOVWreg x:(MOVWreg _)) => (MOVVreg x)
606(MOVWUreg x:(MOVBUreg _)) => (MOVVreg x)
607(MOVWUreg x:(MOVHUreg _)) => (MOVVreg x)
608(MOVWUreg x:(MOVWUreg _)) => (MOVVreg x)
609
610// don't extend before store
611(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
612(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
613(MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
614(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
615(MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
616(MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
617(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
618(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
619(MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
620(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
621(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
622(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
623
624// register indexed load
625(MOVVload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr idx mem)
626(MOVVload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVVloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
627(MOVWUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
628(MOVWUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
629(MOVWload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem)
630(MOVWload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
631(MOVHUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem)
632(MOVHUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
633(MOVHload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem)
634(MOVHload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
635(MOVBUload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem)
636(MOVBUload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
637(MOVBload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem)
638(MOVBload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
639(MOVFload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr idx mem)
640(MOVFload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVFloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
641(MOVDload [off] {sym} (ADDV ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem)
642(MOVDload [off] {sym} (ADDshiftLLV [shift] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr (SLLVconst <typ.Int64> [shift] idx) mem)
643(MOVVloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem)
644(MOVVloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVVload [int32(c)] ptr mem)
645(MOVWUloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
646(MOVWUloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
647(MOVWloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem)
648(MOVWloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem)
649(MOVHUloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
650(MOVHUloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
651(MOVHloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem)
652(MOVHloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem)
653(MOVBUloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
654(MOVBUloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
655(MOVBloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem)
656(MOVBloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem)
657(MOVFloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVFload [int32(c)] ptr mem)
658(MOVFloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVFload [int32(c)] ptr mem)
659(MOVDloadidx ptr (MOVVconst [c]) mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem)
660(MOVDloadidx (MOVVconst [c]) ptr mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem)
661
662// register indexed store
663(MOVVstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr idx val mem)
664(MOVVstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVVstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
665(MOVWstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem)
666(MOVWstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
667(MOVHstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem)
668(MOVHstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
669(MOVBstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem)
670(MOVBstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
671(MOVFstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr idx val mem)
672(MOVFstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVFstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
673(MOVDstore [off] {sym} (ADDV ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem)
674(MOVDstore [off] {sym} (ADDshiftLLV [shift] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr (SLLVconst <typ.Int64> [shift] idx) val mem)
675(MOVVstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVVstore [int32(c)] ptr val mem)
676(MOVVstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVVstore [int32(c)] idx val mem)
677(MOVWstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVWstore [int32(c)] ptr val mem)
678(MOVWstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVWstore [int32(c)] idx val mem)
679(MOVHstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVHstore [int32(c)] ptr val mem)
680(MOVHstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVHstore [int32(c)] idx val mem)
681(MOVBstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVBstore [int32(c)] ptr val mem)
682(MOVBstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVBstore [int32(c)] idx val mem)
683(MOVFstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVFstore [int32(c)] ptr val mem)
684(MOVFstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVFstore [int32(c)] idx val mem)
685(MOVDstoreidx ptr (MOVVconst [c]) val mem) && is32Bit(c) => (MOVDstore [int32(c)] ptr val mem)
686(MOVDstoreidx (MOVVconst [c]) idx val mem) && is32Bit(c) => (MOVDstore [int32(c)] idx val mem)
687
688// if a register move has only 1 use, just use the same register without emitting instruction
689// MOVVnop doesn't emit instruction, only for ensuring the type.
690(MOVVreg x) && x.Uses == 1 => (MOVVnop x)
691
692// TODO: we should be able to get rid of MOVVnop all together.
693// But for now, this is enough to get rid of lots of them.
694(MOVVnop (MOVVconst [c])) => (MOVVconst [c])
695
696// fold constant into arithmetic ops
697(ADDV x (MOVVconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDVconst [c] x)
698(SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
699(AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
700(OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x)
701(XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
702(NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x)
703
704(SLL _ (MOVVconst [c])) && uint64(c)>=32 => (MOVVconst [0])
705(SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
706(SRL _ (MOVVconst [c])) && uint64(c)>=32 => (MOVVconst [0])
707(SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
708(SRA x (MOVVconst [c])) && uint64(c)>=32 => (SRAconst x [31])
709(SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63])
710(SLL x (MOVVconst [c])) && uint64(c) >=0 && uint64(c) <=31 => (SLLconst x [c])
711(SLLV x (MOVVconst [c])) => (SLLVconst x [c])
712(SRL x (MOVVconst [c])) && uint64(c) >=0 && uint64(c) <=31 => (SRLconst x [c])
713(SRLV x (MOVVconst [c])) => (SRLVconst x [c])
714(SRA x (MOVVconst [c])) && uint64(c) >=0 && uint64(c) <=31 => (SRAconst x [c])
715(SRAV x (MOVVconst [c])) => (SRAVconst x [c])
716(ROTR x (MOVVconst [c])) => (ROTRconst x [c&31])
717(ROTRV x (MOVVconst [c])) => (ROTRVconst x [c&63])
718
719// SLLV/SRLV/SRAV only considers the bottom 6 bits of y, similarly SLL/SRL/SRA only considers the
720// bottom 5 bits of y.
721(SLL x (ANDconst [31] y)) => (SLL x y)
722(SRL x (ANDconst [31] y)) => (SRL x y)
723(SRA x (ANDconst [31] y)) => (SRA x y)
724(SLLV x (ANDconst [63] y)) => (SLLV x y)
725(SRLV x (ANDconst [63] y)) => (SRLV x y)
726(SRAV x (ANDconst [63] y)) => (SRAV x y)
727
728// Avoid unnecessary zero and sign extension when right shifting.
729(SRLVconst [rc] (MOVWUreg y)) && rc >= 0 && rc <= 31 => (SRLconst [int64(rc)] y)
730(SRAVconst [rc] (MOVWreg y)) && rc >= 0 && rc <= 31 => (SRAconst [int64(rc)] y)
731
732// Replace right shifts that exceed size of signed type.
733(SRAVconst <t> [rc] (MOVBreg y)) && rc >= 8 => (SRAVconst [63] (SLLVconst <t> [56] y))
734(SRAVconst <t> [rc] (MOVHreg y)) && rc >= 16 => (SRAVconst [63] (SLLVconst <t> [48] y))
735(SRAVconst <t> [rc] (MOVWreg y)) && rc >= 32 => (SRAconst [31] y)
736
737// If the shift amount is larger than the datasize(32, 16, 8), we can optimize to constant 0.
738(MOVWUreg (SLLVconst [lc] x)) && lc >= 32 => (MOVVconst [0])
739(MOVHUreg (SLLVconst [lc] x)) && lc >= 16 => (MOVVconst [0])
740(MOVBUreg (SLLVconst [lc] x)) && lc >= 8 => (MOVVconst [0])
741
742// After zero extension, the upper (64-datasize(32|16|8)) bits are zero, we can optimize to constant 0.
743(SRLVconst [rc] (MOVWUreg x)) && rc >= 32 => (MOVVconst [0])
744(SRLVconst [rc] (MOVHUreg x)) && rc >= 16 => (MOVVconst [0])
745(SRLVconst [rc] (MOVBUreg x)) && rc >= 8 => (MOVVconst [0])
746
747// (x + x) << c -> x << c+1
748((SLLV|SLL)const <t> [c] (ADDV x x)) && c < t.Size() * 8 - 1 => ((SLLV|SLL)const [c+1] x)
749((SLLV|SLL)const <t> [c] (ADDV x x)) && c >= t.Size() * 8 - 1 => (MOVVconst [0])
750
751// mul by constant
752(MULV _ (MOVVconst [0])) => (MOVVconst [0])
753(MULV x (MOVVconst [1])) => x
754
755(MULV x (MOVVconst [c])) && canMulStrengthReduce(config, c) => {mulStrengthReduce(v, x, c)}
756
757(ADDV x0 x1:(SLLVconst [c] y)) && x1.Uses == 1 && c > 0 && c <= 4 => (ADDshiftLLV x0 y [c])
758
759// fold constant in ADDshift op
760(ADDshiftLLV x (MOVVconst [c]) [d]) && is12Bit(c<<d) => (ADDVconst x [c<<d])
761
762// div by constant
763(DIVVU x (MOVVconst [1])) => x
764(DIVVU x (MOVVconst [c])) && isPowerOfTwo(c) => (SRLVconst [log64(c)] x)
765(REMVU _ (MOVVconst [1])) => (MOVVconst [0]) // mod
766(REMVU x (MOVVconst [c])) && isPowerOfTwo(c) => (ANDconst [c-1] x) // mod
767
768// FMA
769(FMA ...) => (FMADDD ...)
770((ADD|SUB)F (MULF x y) z) && z.Block.Func.useFMA(v) => (FM(ADD|SUB)F x y z)
771((ADD|SUB)D (MULD x y) z) && z.Block.Func.useFMA(v) => (FM(ADD|SUB)D x y z)
772// z - xy -> -(xy - z)
773(SUBF z (MULF x y)) && z.Block.Func.useFMA(v) => (FNMSUBF x y z)
774(SUBD z (MULD x y)) && z.Block.Func.useFMA(v) => (FNMSUBD x y z)
775// z + (-xy) -> -(xy - z)
776// z - (-xy) -> xy + z
777((ADD|SUB)F z (NEGF (MULF x y))) && z.Block.Func.useFMA(v) => (F(NMSUB|MADD)F x y z)
778((ADD|SUB)D z (NEGD (MULD x y))) && z.Block.Func.useFMA(v) => (F(NMSUB|MADD)D x y z)
779// -xy - z -> -(xy + z)
780(SUBF (NEGF (MULF x y)) z) && z.Block.Func.useFMA(v) => (FNMADDF x y z)
781(SUBD (NEGD (MULD x y)) z) && z.Block.Func.useFMA(v) => (FNMADDD x y z)
782
783// Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit.
784(MOVDF ((ABS|SQRT)D (MOVFD x))) => ((ABS|SQRT)F x)
785
786// generic simplifications
787(ADDV x (NEGV y)) => (SUBV x y)
788(SUBV x (NEGV y)) => (ADDV x y)
789(SUBV x x) => (MOVVconst [0])
790(SUBV (MOVVconst [0]) x) => (NEGV x)
791(AND x x) => x
792(OR x x) => x
793(XOR x x) => (MOVVconst [0])
794(ORN x (MOVVconst [-1])) => x
795(AND x (NORconst [0] y)) => (ANDN x y)
796(OR x (NORconst [0] y)) => (ORN x y)
797
798// Fold negation into subtraction.
799(NEGV (SUBV x y)) => (SUBV y x)
800(NEGV <t> s:(ADDVconst [c] (SUBV x y))) && s.Uses == 1 && is12Bit(-c) => (ADDVconst [-c] (SUBV <t> y x))
801
802// Double negation.
803(NEGV (NEGV x)) => x
804// Fold NEGV into ADDVconst. Take care to keep c in 12 bit range.
805(NEGV <t> s:(ADDVconst [c] (NEGV x))) && s.Uses == 1 && is12Bit(-c) => (ADDVconst [-c] x)
806
807// remove redundant *const ops
808(ADDVconst [0] x) => x
809(SUBVconst [0] x) => x
810(ANDconst [0] _) => (MOVVconst [0])
811(ANDconst [-1] x) => x
812(ORconst [0] x) => x
813(ORconst [-1] _) => (MOVVconst [-1])
814(XORconst [0] x) => x
815(XORconst [-1] x) => (NORconst [0] x)
816(MASKEQZ (MOVVconst [0]) cond) => (MOVVconst [0])
817(MASKNEZ (MOVVconst [0]) cond) => (MOVVconst [0])
818(MASKEQZ x (MOVVconst [c])) && c == 0 => (MOVVconst [0])
819(MASKEQZ x (MOVVconst [c])) && c != 0 => x
820
821// generic constant folding
822(ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d])
823(ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) => (ADDVconst [c+d] x)
824(ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) => (ADDVconst [c-d] x)
825(SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c])
826(SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) => (ADDVconst [-c-d] x)
827(SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) => (ADDVconst [-c+d] x)
828(SUBV (MOVVconst [c]) (NEGV (SUBVconst [d] x))) => (ADDVconst [c-d] x)
829(ADDVconst [c] x) && is32Bit(c) && c&0xffff == 0 && c != 0 => (ADDV16const [c] x)
830(SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)])
831(SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))])
832(SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)])
833(MULV (MOVVconst [c]) (MOVVconst [d])) => (MOVVconst [c*d])
834(DIVV (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [c/d])
835(DIVVU (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [int64(uint64(c)/uint64(d))])
836(REMV (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [c%d]) // mod
837(REMVU (MOVVconst [c]) (MOVVconst [d])) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
838(ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d])
839(ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
840(ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d])
841(ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x)
842(XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
843(XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x)
844(NORconst [c] (MOVVconst [d])) => (MOVVconst [^(c|d)])
845(NEGV (MOVVconst [c])) => (MOVVconst [-c])
846(MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))])
847(MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))])
848(MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))])
849(MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))])
850(MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))])
851(MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))])
852(MOVVreg (MOVVconst [c])) => (MOVVconst [c])
853
854(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
855
856// Avoid extending when already sufficiently shifted.
857(MOVBUreg x:(SRLconst [c] y)) && c >= 24 => x
858(MOVHUreg x:(SRLconst [c] y)) && c >= 16 => x
859(MOVWUreg x:(SRLconst [c] y)) => x
860
861// Avoid extending when already sufficiently masked.
862(MOVBreg x:(ANDconst [c] y)) && c >= 0 && int64(int8(c)) == c => x
863(MOVHreg x:(ANDconst [c] y)) && c >= 0 && int64(int16(c)) == c => x
864(MOVWreg x:(ANDconst [c] y)) && c >= 0 && int64(int32(c)) == c => x
865(MOVBUreg x:(ANDconst [c] y)) && c >= 0 && int64(uint8(c)) == c => x
866(MOVHUreg x:(ANDconst [c] y)) && c >= 0 && int64(uint16(c)) == c => x
867(MOVWUreg x:(ANDconst [c] y)) && c >= 0 && int64(uint32(c)) == c => x
868
869// Prefetch instructions (hint specified using aux field)
870// For PRELD{,X} A value of hint indicates:
871// hint=0 is defined as load prefetch to L1-cache
872// hint=2 is defined as load prefetch to L3-cache
873// The PrefetchCacheStreamed implementation prefetches 512 bytes of data
874// into L3. The aux field are defined as follows:
875// bit[4:0]:
876// $hint parameter of PRELDX instruction
877// bit[41:5]:
878// $n parameter of PRELDX instruction, bit[0] of $n is the address
879// sequence, bits[11:1] is the block size, bits[20:12] is the block
880// num, bits[36:21] is the stride, for more details about $n, refer
881// to src/cmd/internal/obj/loong64/doc.go
882(PrefetchCache addr mem) => (PRELD addr mem [0])
883(PrefetchCacheStreamed addr mem) => (PRELDX addr mem [(((512 << 1) + (1 << 12)) << 5) + 2])
884
885// constant comparisons
886(SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1])
887(SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0])
888(SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1])
889(SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0])
890
891// other known comparisons
892(SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1])
893(SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0])
894(SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1])
895(SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0])
896(SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1])
897(SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1])
898(SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0])
899(SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1])
900(SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0])
901(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1])
902(SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0])
903(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1])
904(SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1])
905(SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
906(SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
907
908// SGT/SGTU with known outcomes.
909(SGT x x) => (MOVVconst [0])
910(SGTU x x) => (MOVVconst [0])
911
912// Optimizations
913
914// Absorb boolean tests into block
915(NEZ (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
916(NEZ (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
917(EQZ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
918(EQZ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
919(NEZ (XORconst [1] cmp:(SGT _ _)) yes no) => (EQZ cmp yes no)
920(NEZ (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQZ cmp yes no)
921(NEZ (XORconst [1] cmp:(SGTconst _)) yes no) => (EQZ cmp yes no)
922(NEZ (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQZ cmp yes no)
923(EQZ (XORconst [1] cmp:(SGT _ _)) yes no) => (NEZ cmp yes no)
924(EQZ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NEZ cmp yes no)
925(EQZ (XORconst [1] cmp:(SGTconst _)) yes no) => (NEZ cmp yes no)
926(EQZ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NEZ cmp yes no)
927(NEZ (SGTUconst [1] x) yes no) => (EQZ x yes no)
928(EQZ (SGTUconst [1] x) yes no) => (NEZ x yes no)
929(NEZ (SGTU x (MOVVconst [0])) yes no) => (NEZ x yes no)
930(EQZ (SGTU x (MOVVconst [0])) yes no) => (EQZ x yes no)
931(NEZ (SGTconst [0] x) yes no) => (LTZ x yes no)
932(EQZ (SGTconst [0] x) yes no) => (GEZ x yes no)
933(NEZ (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no)
934(EQZ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no)
935
936// Convert EQZ/NEZ into more optimal branch conditions.
937(EQZ (SGTU (MOVVconst [c]) y) yes no) && c >= -2048 && c <= 2047 => (EQZ (SGTUconst [c] y) yes no)
938(NEZ (SGTU (MOVVconst [c]) y) yes no) && c >= -2048 && c <= 2047 => (NEZ (SGTUconst [c] y) yes no)
939(EQZ (SUBV x y) yes no) => (BEQ x y yes no)
940(NEZ (SUBV x y) yes no) => (BNE x y yes no)
941(EQZ (SGT x y) yes no) => (BGE y x yes no)
942(NEZ (SGT x y) yes no) => (BLT y x yes no)
943(EQZ (SGTU x y) yes no) => (BGEU y x yes no)
944(NEZ (SGTU x y) yes no) => (BLTU y x yes no)
945(EQZ (SGTconst [c] y) yes no) => (BGE y (MOVVconst [c]) yes no)
946(NEZ (SGTconst [c] y) yes no) => (BLT y (MOVVconst [c]) yes no)
947(EQZ (SGTUconst [c] y) yes no) => (BGEU y (MOVVconst [c]) yes no)
948(NEZ (SGTUconst [c] y) yes no) => (BLTU y (MOVVconst [c]) yes no)
949
950// absorb constants into branches
951(EQZ (MOVVconst [0]) yes no) => (First yes no)
952(EQZ (MOVVconst [c]) yes no) && c != 0 => (First no yes)
953(NEZ (MOVVconst [0]) yes no) => (First no yes)
954(NEZ (MOVVconst [c]) yes no) && c != 0 => (First yes no)
955(LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no)
956(LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes)
957(LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no)
958(LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes)
959(GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no)
960(GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes)
961(GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
962(GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
963
964// absorb NEGV into branches
965(EQZ (NEGV x) yes no) => (EQZ x yes no)
966(NEZ (NEGV x) yes no) => (NEZ x yes no)
967
968// Convert branch with zero to more optimal branch zero.
969(BEQ (MOVVconst [0]) cond yes no) => (EQZ cond yes no)
970(BEQ cond (MOVVconst [0]) yes no) => (EQZ cond yes no)
971(BNE (MOVVconst [0]) cond yes no) => (NEZ cond yes no)
972(BNE cond (MOVVconst [0]) yes no) => (NEZ cond yes no)
973(BLT (MOVVconst [0]) cond yes no) => (GTZ cond yes no)
974(BLT cond (MOVVconst [0]) yes no) => (LTZ cond yes no)
975(BLTU (MOVVconst [0]) cond yes no) => (NEZ cond yes no)
976(BGE (MOVVconst [0]) cond yes no) => (LEZ cond yes no)
977(BGE cond (MOVVconst [0]) yes no) => (GEZ cond yes no)
978(BGEU (MOVVconst [0]) cond yes no) => (EQZ cond yes no)
979
980// Arch-specific inlining for small or disjoint runtime.memmove
981// Match post-lowering calls, register version.
982(SelectN [0] call:(CALLstatic {sym} dst src (MOVVconst [sz]) mem))
983 && sz >= 0
984 && isSameCall(sym, "runtime.memmove")
985 && call.Uses == 1
986 && isInlinableMemmove(dst, src, sz, config)
987 && clobber(call)
988 => (Move [sz] dst src mem)
989
990// fold readonly sym load
991(MOVBUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read8(sym, int64(off)))])
992(MOVHUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
993(MOVWUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
994(MOVVload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
995(MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int8(read8(sym, int64(off))))])
996(MOVHload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
997(MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
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