1// Copyright 2016 The Go Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style
3// license that can be found in the LICENSE file.
4
5(Add(Ptr|64|32|16|8) ...) => (ADDV ...)
6(Add(32|64)F ...) => (ADD(F|D) ...)
7
8(Sub(Ptr|64|32|16|8) ...) => (SUBV ...)
9(Sub(32|64)F ...) => (SUB(F|D) ...)
10
11(Mul(64|32|16|8) x y) => (Select1 (MULVU x y))
12(Mul(32|64)F ...) => (MUL(F|D) ...)
13(Mul64uhilo ...) => (MULVU ...)
14(Select0 (Mul64uover x y)) => (Select1 <typ.UInt64> (MULVU x y))
15(Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (Select0 <typ.UInt64> (MULVU x y)) (MOVVconst <typ.UInt64> [0]))
16
17(Hmul64 x y) => (Select0 (MULV x y))
18(Hmul64u x y) => (Select0 (MULVU x y))
19(Hmul32 x y) => (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32])
20(Hmul32u x y) => (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32])
21
22(Div64 x y) => (Select1 (DIVV x y))
23(Div64u x y) => (Select1 (DIVVU x y))
24(Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
25(Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
26(Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
27(Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
28(Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
29(Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
30(Div(32|64)F ...) => (DIV(F|D) ...)
31
32(Mod64 x y) => (Select0 (DIVV x y))
33(Mod64u x y) => (Select0 (DIVVU x y))
34(Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
35(Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
36(Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
37(Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
38(Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
39(Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
40
41(Select0 <t> (Add64carry x y c)) => (ADDV (ADDV <t> x y) c)
42(Select1 <t> (Add64carry x y c)) =>
43 (OR (SGTU <t> x s:(ADDV <t> x y)) (SGTU <t> s (ADDV <t> s c)))
44
45(Select0 <t> (Sub64borrow x y c)) => (SUBV (SUBV <t> x y) c)
46(Select1 <t> (Sub64borrow x y c)) =>
47 (OR (SGTU <t> s:(SUBV <t> x y) x) (SGTU <t> (SUBV <t> s c) s))
48
49// math package intrinsics
50(Abs ...) => (ABSD ...)
51
52// (x + y) / 2 with x>=y => (x - y) / 2 + y
53(Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
54
55(And(64|32|16|8) ...) => (AND ...)
56(Or(64|32|16|8) ...) => (OR ...)
57(Xor(64|32|16|8) ...) => (XOR ...)
58
59// shifts
60// hardware instruction uses only the low 6 bits of the shift
61// we compare to 64 to ensure Go semantics for large shifts
62(Lsh64x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
63(Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
64(Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
65(Lsh64x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
66
67(Lsh32x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
68(Lsh32x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
69(Lsh32x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
70(Lsh32x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
71
72(Lsh16x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
73(Lsh16x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
74(Lsh16x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
75(Lsh16x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
76
77(Lsh8x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
78(Lsh8x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
79(Lsh8x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
80(Lsh8x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
81
82(Rsh64Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y))
83(Rsh64Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y)))
84(Rsh64Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y)))
85(Rsh64Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y)))
86
87(Rsh32Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y))
88(Rsh32Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y)))
89(Rsh32Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y)))
90(Rsh32Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y)))
91
92(Rsh16Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y))
93(Rsh16Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y)))
94(Rsh16Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y)))
95(Rsh16Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y)))
96
97(Rsh8Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y))
98(Rsh8Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y)))
99(Rsh8Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y)))
100(Rsh8Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y)))
101
102(Rsh64x64 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
103(Rsh64x32 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
104(Rsh64x16 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
105(Rsh64x8 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
106
107(Rsh32x64 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
108(Rsh32x32 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
109(Rsh32x16 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
110(Rsh32x8 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
111
112(Rsh16x64 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
113(Rsh16x32 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
114(Rsh16x16 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
115(Rsh16x8 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
116
117(Rsh8x64 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
118(Rsh8x32 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
119(Rsh8x16 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
120(Rsh8x8 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
121
122// rotates
123(RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
124(RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
125(RotateLeft32 <t> x (MOVVconst [c])) => (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
126(RotateLeft64 <t> x (MOVVconst [c])) => (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
127
128// unary ops
129(Neg(64|32|16|8) ...) => (NEGV ...)
130(Neg(32|64)F ...) => (NEG(F|D) ...)
131
132(Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
133
134(Sqrt ...) => (SQRTD ...)
135(Sqrt32 ...) => (SQRTF ...)
136
137// boolean ops -- booleans are represented with 0=false, 1=true
138(AndB ...) => (AND ...)
139(OrB ...) => (OR ...)
140(EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
141(NeqB ...) => (XOR ...)
142(Not x) => (XORconst [1] x)
143
144// constants
145(Const(64|32|16|8) [val]) => (MOVVconst [int64(val)])
146(Const(32|64)F [val]) => (MOV(F|D)const [float64(val)])
147(ConstNil) => (MOVVconst [0])
148(ConstBool [t]) => (MOVVconst [int64(b2i(t))])
149
150(Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63])
151
152// truncations
153// Because we ignore high parts of registers, truncates are just copies.
154(Trunc16to8 ...) => (Copy ...)
155(Trunc32to8 ...) => (Copy ...)
156(Trunc32to16 ...) => (Copy ...)
157(Trunc64to8 ...) => (Copy ...)
158(Trunc64to16 ...) => (Copy ...)
159(Trunc64to32 ...) => (Copy ...)
160
161// Zero-/Sign-extensions
162(ZeroExt8to16 ...) => (MOVBUreg ...)
163(ZeroExt8to32 ...) => (MOVBUreg ...)
164(ZeroExt16to32 ...) => (MOVHUreg ...)
165(ZeroExt8to64 ...) => (MOVBUreg ...)
166(ZeroExt16to64 ...) => (MOVHUreg ...)
167(ZeroExt32to64 ...) => (MOVWUreg ...)
168
169(SignExt8to16 ...) => (MOVBreg ...)
170(SignExt8to32 ...) => (MOVBreg ...)
171(SignExt16to32 ...) => (MOVHreg ...)
172(SignExt8to64 ...) => (MOVBreg ...)
173(SignExt16to64 ...) => (MOVHreg ...)
174(SignExt32to64 ...) => (MOVWreg ...)
175
176// float <=> int conversion
177(Cvt32to32F ...) => (MOVWF ...)
178(Cvt32to64F ...) => (MOVWD ...)
179(Cvt64to32F ...) => (MOVVF ...)
180(Cvt64to64F ...) => (MOVVD ...)
181(Cvt32Fto32 ...) => (TRUNCFW ...)
182(Cvt64Fto32 ...) => (TRUNCDW ...)
183(Cvt32Fto64 ...) => (TRUNCFV ...)
184(Cvt64Fto64 ...) => (TRUNCDV ...)
185(Cvt32Fto64F ...) => (MOVFD ...)
186(Cvt64Fto32F ...) => (MOVDF ...)
187
188(CvtBoolToUint8 ...) => (Copy ...)
189
190(Round(32|64)F ...) => (Copy ...)
191
192// comparisons
193(Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
194(Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
195(Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
196(Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
197(EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
198(Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
199
200(Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0]))
201(Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0]))
202(Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0]))
203(Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0]))
204(NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0]))
205(Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
206
207(Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x))
208(Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x))
209(Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x))
210(Less64 x y) => (SGT y x)
211(Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
212
213(Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))
214(Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))
215(Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))
216(Less64U x y) => (SGTU y x)
217
218(Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y)))
219(Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y)))
220(Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y)))
221(Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y))
222(Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
223
224(Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)))
225(Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)))
226(Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)))
227(Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y))
228
229(OffPtr [off] ptr:(SP)) && is32Bit(off) => (MOVVaddr [int32(off)] ptr)
230(OffPtr [off] ptr) && is32Bit(off) => (ADDVconst [off] ptr)
231(OffPtr [off] ptr) && !is32Bit(off) => (ADDV ptr (MOVVconst <typ.UInt64> [off]))
232
233(Addr {sym} base) => (MOVVaddr {sym} base)
234(LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVVaddr {sym} (SPanchored base mem))
235(LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVVaddr {sym} base)
236
237// loads
238(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
239(Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
240(Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
241(Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
242(Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
243(Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
244(Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
245(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
246(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
247(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
248
249// stores
250(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
251(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
252(Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
253(Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVVstore ptr val mem)
254(Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
255(Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
256
257// zeroing
258(Zero [0] _ mem) => mem
259(Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem)
260(Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
261 (MOVHstore ptr (MOVVconst [0]) mem)
262(Zero [2] ptr mem) =>
263 (MOVBstore [1] ptr (MOVVconst [0])
264 (MOVBstore [0] ptr (MOVVconst [0]) mem))
265(Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
266 (MOVWstore ptr (MOVVconst [0]) mem)
267(Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
268 (MOVHstore [2] ptr (MOVVconst [0])
269 (MOVHstore [0] ptr (MOVVconst [0]) mem))
270(Zero [4] ptr mem) =>
271 (MOVBstore [3] ptr (MOVVconst [0])
272 (MOVBstore [2] ptr (MOVVconst [0])
273 (MOVBstore [1] ptr (MOVVconst [0])
274 (MOVBstore [0] ptr (MOVVconst [0]) mem))))
275(Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 =>
276 (MOVVstore ptr (MOVVconst [0]) mem)
277(Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
278 (MOVWstore [4] ptr (MOVVconst [0])
279 (MOVWstore [0] ptr (MOVVconst [0]) mem))
280(Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 =>
281 (MOVHstore [6] ptr (MOVVconst [0])
282 (MOVHstore [4] ptr (MOVVconst [0])
283 (MOVHstore [2] ptr (MOVVconst [0])
284 (MOVHstore [0] ptr (MOVVconst [0]) mem))))
285
286(Zero [3] ptr mem) =>
287 (MOVBstore [2] ptr (MOVVconst [0])
288 (MOVBstore [1] ptr (MOVVconst [0])
289 (MOVBstore [0] ptr (MOVVconst [0]) mem)))
290(Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
291 (MOVHstore [4] ptr (MOVVconst [0])
292 (MOVHstore [2] ptr (MOVVconst [0])
293 (MOVHstore [0] ptr (MOVVconst [0]) mem)))
294(Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
295 (MOVWstore [8] ptr (MOVVconst [0])
296 (MOVWstore [4] ptr (MOVVconst [0])
297 (MOVWstore [0] ptr (MOVVconst [0]) mem)))
298(Zero [16] {t} ptr mem) && t.Alignment()%8 == 0 =>
299 (MOVVstore [8] ptr (MOVVconst [0])
300 (MOVVstore [0] ptr (MOVVconst [0]) mem))
301(Zero [24] {t} ptr mem) && t.Alignment()%8 == 0 =>
302 (MOVVstore [16] ptr (MOVVconst [0])
303 (MOVVstore [8] ptr (MOVVconst [0])
304 (MOVVstore [0] ptr (MOVVconst [0]) mem)))
305
306// medium zeroing uses a duff device
307// 8, and 128 are magic constants, see runtime/mkduff.go
308(Zero [s] {t} ptr mem)
309 && s%8 == 0 && s > 24 && s <= 8*128
310 && t.Alignment()%8 == 0 =>
311 (DUFFZERO [8 * (128 - s/8)] ptr mem)
312
313// large or unaligned zeroing uses a loop
314(Zero [s] {t} ptr mem)
315 && s > 8*128 || t.Alignment()%8 != 0 =>
316 (LoweredZero [t.Alignment()]
317 ptr
318 (ADDVconst <ptr.Type> ptr [s-moveSize(t.Alignment(), config)])
319 mem)
320
321// moves
322(Move [0] _ _ mem) => mem
323(Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
324(Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
325 (MOVHstore dst (MOVHload src mem) mem)
326(Move [2] dst src mem) =>
327 (MOVBstore [1] dst (MOVBload [1] src mem)
328 (MOVBstore dst (MOVBload src mem) mem))
329(Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
330 (MOVWstore dst (MOVWload src mem) mem)
331(Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
332 (MOVHstore [2] dst (MOVHload [2] src mem)
333 (MOVHstore dst (MOVHload src mem) mem))
334(Move [4] dst src mem) =>
335 (MOVBstore [3] dst (MOVBload [3] src mem)
336 (MOVBstore [2] dst (MOVBload [2] src mem)
337 (MOVBstore [1] dst (MOVBload [1] src mem)
338 (MOVBstore dst (MOVBload src mem) mem))))
339(Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
340 (MOVVstore dst (MOVVload src mem) mem)
341(Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
342 (MOVWstore [4] dst (MOVWload [4] src mem)
343 (MOVWstore dst (MOVWload src mem) mem))
344(Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
345 (MOVHstore [6] dst (MOVHload [6] src mem)
346 (MOVHstore [4] dst (MOVHload [4] src mem)
347 (MOVHstore [2] dst (MOVHload [2] src mem)
348 (MOVHstore dst (MOVHload src mem) mem))))
349
350(Move [3] dst src mem) =>
351 (MOVBstore [2] dst (MOVBload [2] src mem)
352 (MOVBstore [1] dst (MOVBload [1] src mem)
353 (MOVBstore dst (MOVBload src mem) mem)))
354(Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
355 (MOVHstore [4] dst (MOVHload [4] src mem)
356 (MOVHstore [2] dst (MOVHload [2] src mem)
357 (MOVHstore dst (MOVHload src mem) mem)))
358(Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
359 (MOVWstore [8] dst (MOVWload [8] src mem)
360 (MOVWstore [4] dst (MOVWload [4] src mem)
361 (MOVWstore dst (MOVWload src mem) mem)))
362(Move [16] {t} dst src mem) && t.Alignment()%8 == 0 =>
363 (MOVVstore [8] dst (MOVVload [8] src mem)
364 (MOVVstore dst (MOVVload src mem) mem))
365(Move [24] {t} dst src mem) && t.Alignment()%8 == 0 =>
366 (MOVVstore [16] dst (MOVVload [16] src mem)
367 (MOVVstore [8] dst (MOVVload [8] src mem)
368 (MOVVstore dst (MOVVload src mem) mem)))
369
370// float <=> int register moves, with no conversion.
371// These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}.
372(MOVVload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (MOVVfpgp val)
373(MOVDload [off] {sym} ptr (MOVVstore [off] {sym} ptr val _)) => (MOVVgpfp val)
374(MOVWUload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (ZeroExt32to64 (MOVWfpgp <typ.Float32> val))
375(MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
376
377// Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
378(MOVVstore [off] {sym} ptr (MOVVfpgp val) mem) => (MOVDstore [off] {sym} ptr val mem)
379(MOVDstore [off] {sym} ptr (MOVVgpfp val) mem) => (MOVVstore [off] {sym} ptr val mem)
380(MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) => (MOVFstore [off] {sym} ptr val mem)
381(MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
382
383// medium move uses a duff device
384(Move [s] {t} dst src mem)
385 && s%8 == 0 && s >= 24 && s <= 8*128 && t.Alignment()%8 == 0
386 && logLargeCopy(v, s) =>
387 (DUFFCOPY [16 * (128 - s/8)] dst src mem)
388// 16 and 128 are magic constants. 16 is the number of bytes to encode:
389// MOVV (R1), R23
390// ADDV $8, R1
391// MOVV R23, (R2)
392// ADDV $8, R2
393// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.
394
395// large or unaligned move uses a loop
396(Move [s] {t} dst src mem)
397 && s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0 =>
398 (LoweredMove [t.Alignment()]
399 dst
400 src
401 (ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)])
402 mem)
403
404// calls
405(StaticCall ...) => (CALLstatic ...)
406(ClosureCall ...) => (CALLclosure ...)
407(InterCall ...) => (CALLinter ...)
408(TailCall ...) => (CALLtail ...)
409(TailCallInter ...) => (CALLtailinter ...)
410
411// atomic intrinsics
412(AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...)
413(AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...)
414
415(AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...)
416(AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...)
417
418(AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
419
420(AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
421
422(AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem)
423(AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...)
424
425// AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << ((ptr & 3) * 8))
426(AtomicOr8 ptr val mem) && !config.BigEndian =>
427 (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
428 (SLLV <typ.UInt32> (ZeroExt8to32 val)
429 (SLLVconst <typ.UInt64> [3]
430 (ANDconst <typ.UInt64> [3] ptr))) mem)
431
432// AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
433(AtomicAnd8 ptr val mem) && !config.BigEndian =>
434 (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
435 (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
436 (SLLVconst <typ.UInt64> [3]
437 (ANDconst <typ.UInt64> [3] ptr)))
438 (NOR (MOVVconst [0]) <typ.UInt64> (SLLV <typ.UInt64>
439 (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
440 (ANDconst <typ.UInt64> [3] ptr))))) mem)
441
442// AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
443(AtomicOr8 ptr val mem) && config.BigEndian =>
444 (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
445 (SLLV <typ.UInt32> (ZeroExt8to32 val)
446 (SLLVconst <typ.UInt64> [3]
447 (ANDconst <typ.UInt64> [3]
448 (XORconst <typ.UInt64> [3] ptr)))) mem)
449
450// AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
451(AtomicAnd8 ptr val mem) && config.BigEndian =>
452 (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
453 (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
454 (SLLVconst <typ.UInt64> [3]
455 (ANDconst <typ.UInt64> [3]
456 (XORconst <typ.UInt64> [3] ptr))))
457 (NOR (MOVVconst [0]) <typ.UInt64> (SLLV <typ.UInt64>
458 (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
459 (ANDconst <typ.UInt64> [3]
460 (XORconst <typ.UInt64> [3] ptr)))))) mem)
461
462(AtomicAnd32 ...) => (LoweredAtomicAnd32 ...)
463(AtomicOr32 ...) => (LoweredAtomicOr32 ...)
464
465// checks
466(NilCheck ...) => (LoweredNilCheck ...)
467(IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
468(IsInBounds idx len) => (SGTU len idx)
469(IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
470
471// pseudo-ops
472(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
473(GetCallerSP ...) => (LoweredGetCallerSP ...)
474(GetCallerPC ...) => (LoweredGetCallerPC ...)
475
476(If cond yes no) => (NE cond yes no)
477
478// Write barrier.
479(WB ...) => (LoweredWB ...)
480
481// Publication barrier as intrinsic
482(PubBarrier ...) => (LoweredPubBarrier ...)
483
484(PanicBounds ...) => (LoweredPanicBoundsRR ...)
485(LoweredPanicBoundsRR [kind] x (MOVVconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem)
486(LoweredPanicBoundsRR [kind] (MOVVconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem)
487(LoweredPanicBoundsRC [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem)
488(LoweredPanicBoundsCR [kind] {p} (MOVVconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem)
489
490// Optimizations
491
492// Absorb boolean tests into block
493(NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
494(NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
495(EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
496(EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
497(NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
498(NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
499(NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
500(NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
501(EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
502(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
503(EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
504(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
505(NE (SGTUconst [1] x) yes no) => (EQ x yes no)
506(EQ (SGTUconst [1] x) yes no) => (NE x yes no)
507(NE (SGTU x (MOVVconst [0])) yes no) => (NE x yes no)
508(EQ (SGTU x (MOVVconst [0])) yes no) => (EQ x yes no)
509(NE (SGTconst [0] x) yes no) => (LTZ x yes no)
510(EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
511(NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no)
512(EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no)
513
514// fold offset into address
515(ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr)
516
517// fold address into load/store
518(MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
519 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVBload [off1+int32(off2)] {sym} ptr mem)
520(MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
521 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVBUload [off1+int32(off2)] {sym} ptr mem)
522(MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
523 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVHload [off1+int32(off2)] {sym} ptr mem)
524(MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
525 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVHUload [off1+int32(off2)] {sym} ptr mem)
526(MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
527 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVWload [off1+int32(off2)] {sym} ptr mem)
528(MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
529 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVWUload [off1+int32(off2)] {sym} ptr mem)
530(MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
531 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVVload [off1+int32(off2)] {sym} ptr mem)
532(MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
533 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVFload [off1+int32(off2)] {sym} ptr mem)
534(MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
535 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVDload [off1+int32(off2)] {sym} ptr mem)
536
537(MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
538 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
539(MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
540 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
541(MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
542 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
543(MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
544 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVVstore [off1+int32(off2)] {sym} ptr val mem)
545(MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
546 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVFstore [off1+int32(off2)] {sym} ptr val mem)
547(MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
548 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) => (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
549
550(MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
551 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
552 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
553 (MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
554(MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
555 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
556 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
557 (MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
558(MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
559 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
560 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
561 (MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
562(MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
563 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
564 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
565 (MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
566(MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
567 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
568 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
569 (MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
570(MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
571 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
572 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
573 (MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
574(MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
575 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
576 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
577 (MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
578(MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
579 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
580 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
581 (MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
582(MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem)
583 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
584 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
585 (MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
586
587(MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
588 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
589 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
590 (MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
591(MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
592 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
593 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
594 (MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
595(MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
596 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
597 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
598 (MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
599(MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
600 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
601 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
602 (MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
603(MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
604 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
605 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
606 (MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
607(MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem)
608 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
609 && (ptr.Op != OpSB || !config.ctxt.Flag_shared) =>
610 (MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
611
612// don't extend after proper load
613(MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
614(MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
615(MOVHreg x:(MOVBload _ _)) => (MOVVreg x)
616(MOVHreg x:(MOVBUload _ _)) => (MOVVreg x)
617(MOVHreg x:(MOVHload _ _)) => (MOVVreg x)
618(MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x)
619(MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x)
620(MOVWreg x:(MOVBload _ _)) => (MOVVreg x)
621(MOVWreg x:(MOVBUload _ _)) => (MOVVreg x)
622(MOVWreg x:(MOVHload _ _)) => (MOVVreg x)
623(MOVWreg x:(MOVHUload _ _)) => (MOVVreg x)
624(MOVWreg x:(MOVWload _ _)) => (MOVVreg x)
625(MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x)
626(MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x)
627(MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x)
628
629// fold double extensions
630(MOVBreg x:(MOVBreg _)) => (MOVVreg x)
631(MOVBUreg x:(MOVBUreg _)) => (MOVVreg x)
632(MOVHreg x:(MOVBreg _)) => (MOVVreg x)
633(MOVHreg x:(MOVBUreg _)) => (MOVVreg x)
634(MOVHreg x:(MOVHreg _)) => (MOVVreg x)
635(MOVHUreg x:(MOVBUreg _)) => (MOVVreg x)
636(MOVHUreg x:(MOVHUreg _)) => (MOVVreg x)
637(MOVWreg x:(MOVBreg _)) => (MOVVreg x)
638(MOVWreg x:(MOVBUreg _)) => (MOVVreg x)
639(MOVWreg x:(MOVHreg _)) => (MOVVreg x)
640(MOVWreg x:(MOVWreg _)) => (MOVVreg x)
641(MOVWUreg x:(MOVBUreg _)) => (MOVVreg x)
642(MOVWUreg x:(MOVHUreg _)) => (MOVVreg x)
643(MOVWUreg x:(MOVWUreg _)) => (MOVVreg x)
644
645// don't extend before store
646(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
647(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
648(MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
649(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
650(MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
651(MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
652(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
653(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
654(MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
655(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
656(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
657(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
658
659// if a register move has only 1 use, just use the same register without emitting instruction
660// MOVVnop doesn't emit instruction, only for ensuring the type.
661(MOVVreg x) && x.Uses == 1 => (MOVVnop x)
662
663// TODO: we should be able to get rid of MOVVnop all together.
664// But for now, this is enough to get rid of lots of them.
665(MOVVnop (MOVVconst [c])) => (MOVVconst [c])
666
667// fold constant into arithmetic ops
668(ADDV x (MOVVconst <t> [c])) && is32Bit(c) && !t.IsPtr() => (ADDVconst [c] x)
669(SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
670(AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
671(OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x)
672(XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
673
674(SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
675(SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
676(SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63])
677(SLLV x (MOVVconst [c])) => (SLLVconst x [c])
678(SRLV x (MOVVconst [c])) => (SRLVconst x [c])
679(SRAV x (MOVVconst [c])) => (SRAVconst x [c])
680
681(SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x)
682(SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
683
684// mul by constant
685(Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x)
686(Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0])
687(Select1 (MULVU x (MOVVconst [1]))) => x
688(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (SLLVconst [log64(c)] x)
689
690// div by constant
691(Select1 (DIVVU x (MOVVconst [1]))) => x
692(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (SRLVconst [log64(c)] x)
693(Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod
694(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo(c) => (ANDconst [c-1] x) // mod
695
696// Absorb conversion between 32 bit and 64 bit if both src and dst are 32 bit.
697(MOVDF ((ABS|SQRT)D (MOVFD x))) => ((ABS|SQRT)F x)
698
699// generic simplifications
700(ADDV x (NEGV y)) => (SUBV x y)
701(SUBV x (NEGV y)) => (ADDV x y)
702(SUBV x x) => (MOVVconst [0])
703(SUBV (MOVVconst [0]) x) => (NEGV x)
704(AND x x) => x
705(OR x x) => x
706(XOR x x) => (MOVVconst [0])
707(NEGV (SUBV x y)) => (SUBV y x)
708(NEGV (NEGV x)) => x
709
710// remove redundant *const ops
711(ADDVconst [0] x) => x
712(SUBVconst [0] x) => x
713(ANDconst [0] _) => (MOVVconst [0])
714(ANDconst [-1] x) => x
715(ORconst [0] x) => x
716(ORconst [-1] _) => (MOVVconst [-1])
717(XORconst [0] x) => x
718
719// generic constant folding
720(ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d])
721(ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) => (ADDVconst [c+d] x)
722(ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) => (ADDVconst [c-d] x)
723(SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c])
724(SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) => (ADDVconst [-c-d] x)
725(SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) => (ADDVconst [-c+d] x)
726(SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)])
727(SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))])
728(SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)])
729(Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c*d])
730(Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c/d])
731(Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)/uint64(d))])
732(Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [c%d]) // mod
733(Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) && d != 0 => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
734(ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d])
735(ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
736(ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d])
737(ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x)
738(XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
739(XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x)
740(NEGV (MOVVconst [c])) => (MOVVconst [-c])
741(MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))])
742(MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))])
743(MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))])
744(MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))])
745(MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))])
746(MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))])
747(MOVVreg (MOVVconst [c])) => (MOVVconst [c])
748(LoweredAtomicStore(32|64) ptr (MOVVconst [0]) mem) => (LoweredAtomicStorezero(32|64) ptr mem)
749(LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst32 [int32(c)] ptr mem)
750(LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst64 [c] ptr mem)
751
752// constant comparisons
753(SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1])
754(SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0])
755(SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1])
756(SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0])
757
758// other known comparisons
759(SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1])
760(SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0])
761(SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1])
762(SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0])
763(SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1])
764(SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1])
765(SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0])
766(SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1])
767(SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0])
768(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1])
769(SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0])
770(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1])
771(SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1])
772(SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
773(SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
774
775// absorb constants into branches
776(EQ (MOVVconst [0]) yes no) => (First yes no)
777(EQ (MOVVconst [c]) yes no) && c != 0 => (First no yes)
778(NE (MOVVconst [0]) yes no) => (First no yes)
779(NE (MOVVconst [c]) yes no) && c != 0 => (First yes no)
780(LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no)
781(LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes)
782(LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no)
783(LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes)
784(GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no)
785(GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes)
786(GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
787(GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
788
789// SGT/SGTU with known outcomes.
790(SGT x x) => (MOVVconst [0])
791(SGTU x x) => (MOVVconst [0])
792
793// fold readonly sym load
794(MOVBUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read8(sym, int64(off)))])
795(MOVHUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
796(MOVWUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
797(MOVVload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
798(MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int8(read8(sym, int64(off))))])
799(MOVHload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
800(MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVVconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
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