list7.go

Documentation: cmd/internal/obj/arm64

     1  // cmd/7l/list.c and cmd/7l/sub.c from Vita Nuova.
     2  // https://bitbucket.org/plan9-from-bell-labs/9-cc/src/master/
     3  //
     4  // 	Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
     5  // 	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6  // 	Portions Copyright © 1997-1999 Vita Nuova Limited
     7  // 	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8  // 	Portions Copyright © 2004,2006 Bruce Ellis
     9  // 	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10  // 	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11  // 	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12  //
    13  // Permission is hereby granted, free of charge, to any person obtaining a copy
    14  // of this software and associated documentation files (the "Software"), to deal
    15  // in the Software without restriction, including without limitation the rights
    16  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17  // copies of the Software, and to permit persons to whom the Software is
    18  // furnished to do so, subject to the following conditions:
    19  //
    20  // The above copyright notice and this permission notice shall be included in
    21  // all copies or substantial portions of the Software.
    22  //
    23  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29  // THE SOFTWARE.
    30  
    31  package arm64
    32  
    33  import (
    34  	"cmd/internal/obj"
    35  	"fmt"
    36  )
    37  
    38  var strcond = [16]string{
    39  	"EQ",
    40  	"NE",
    41  	"HS",
    42  	"LO",
    43  	"MI",
    44  	"PL",
    45  	"VS",
    46  	"VC",
    47  	"HI",
    48  	"LS",
    49  	"GE",
    50  	"LT",
    51  	"GT",
    52  	"LE",
    53  	"AL",
    54  	"NV",
    55  }
    56  
    57  func init() {
    58  	obj.RegisterRegister(obj.RBaseARM64, REG_SPECIAL+1024, rconv)
    59  	obj.RegisterOpcode(obj.ABaseARM64, Anames)
    60  	obj.RegisterRegisterList(obj.RegListARM64Lo, obj.RegListARM64Hi, rlconv)
    61  	obj.RegisterOpSuffix("arm64", obj.CConvARM)
    62  	obj.RegisterSpecialOperands(int64(SPOP_BEGIN), int64(SPOP_END), SPCconv)
    63  }
    64  
    65  func arrange(a int) string {
    66  	switch a {
    67  	case ARNG_8B:
    68  		return "B8"
    69  	case ARNG_16B:
    70  		return "B16"
    71  	case ARNG_4H:
    72  		return "H4"
    73  	case ARNG_8H:
    74  		return "H8"
    75  	case ARNG_2S:
    76  		return "S2"
    77  	case ARNG_4S:
    78  		return "S4"
    79  	case ARNG_1D:
    80  		return "D1"
    81  	case ARNG_2D:
    82  		return "D2"
    83  	case ARNG_B:
    84  		return "B"
    85  	case ARNG_H:
    86  		return "H"
    87  	case ARNG_S:
    88  		return "S"
    89  	case ARNG_D:
    90  		return "D"
    91  	case ARNG_1Q:
    92  		return "Q1"
    93  	case ARNG_Q:
    94  		return "Q"
    95  	case PRED_M:
    96  		return "M"
    97  	case PRED_Z:
    98  		return "Z"
    99  	default:
   100  		return ""
   101  	}
   102  }
   103  
   104  func rconv(r int) string {
   105  	ext := (r >> 5) & 7
   106  	if r == REGG {
   107  		return "g"
   108  	}
   109  	switch {
   110  	case REG_R0 <= r && r <= REG_R30:
   111  		return fmt.Sprintf("R%d", r-REG_R0)
   112  	case r == REG_R31:
   113  		return "ZR"
   114  	case REG_F0 <= r && r <= REG_F31:
   115  		return fmt.Sprintf("F%d", r-REG_F0)
   116  	case REG_V0 <= r && r <= REG_V31:
   117  		return fmt.Sprintf("V%d", r-REG_V0)
   118  	case REG_Z0 <= r && r <= REG_Z31:
   119  		return fmt.Sprintf("Z%d", r-REG_Z0)
   120  	case REG_P0 <= r && r <= REG_P15:
   121  		return fmt.Sprintf("P%d", r-REG_P0)
   122  	case REG_PN0 <= r && r <= REG_PN15:
   123  		return fmt.Sprintf("PN%d", r-REG_PN0)
   124  	case r == REGSP:
   125  		return "RSP"
   126  	case REG_UXTB <= r && r < REG_UXTH:
   127  		if ext != 0 {
   128  			return fmt.Sprintf("%s.UXTB<<%d", regname(r), ext)
   129  		} else {
   130  			return fmt.Sprintf("%s.UXTB", regname(r))
   131  		}
   132  	case REG_UXTH <= r && r < REG_UXTW:
   133  		if ext != 0 {
   134  			return fmt.Sprintf("%s.UXTH<<%d", regname(r), ext)
   135  		} else {
   136  			return fmt.Sprintf("%s.UXTH", regname(r))
   137  		}
   138  	case REG_UXTW <= r && r < REG_UXTX:
   139  		if ext != 0 {
   140  			return fmt.Sprintf("%s.UXTW<<%d", regname(r), ext)
   141  		} else {
   142  			return fmt.Sprintf("%s.UXTW", regname(r))
   143  		}
   144  	case REG_UXTX <= r && r < REG_SXTB:
   145  		if ext != 0 {
   146  			return fmt.Sprintf("%s.UXTX<<%d", regname(r), ext)
   147  		} else {
   148  			return fmt.Sprintf("%s.UXTX", regname(r))
   149  		}
   150  	case REG_SXTB <= r && r < REG_SXTH:
   151  		if ext != 0 {
   152  			return fmt.Sprintf("%s.SXTB<<%d", regname(r), ext)
   153  		} else {
   154  			return fmt.Sprintf("%s.SXTB", regname(r))
   155  		}
   156  	case REG_SXTH <= r && r < REG_SXTW:
   157  		if ext != 0 {
   158  			return fmt.Sprintf("%s.SXTH<<%d", regname(r), ext)
   159  		} else {
   160  			return fmt.Sprintf("%s.SXTH", regname(r))
   161  		}
   162  	case REG_SXTW <= r && r < REG_SXTX:
   163  		if ext != 0 {
   164  			return fmt.Sprintf("%s.SXTW<<%d", regname(r), ext)
   165  		} else {
   166  			return fmt.Sprintf("%s.SXTW", regname(r))
   167  		}
   168  	case REG_SXTX <= r && r < REG_SPECIAL:
   169  		if ext != 0 {
   170  			return fmt.Sprintf("%s.SXTX<<%d", regname(r), ext)
   171  		} else {
   172  			return fmt.Sprintf("%s.SXTX", regname(r))
   173  		}
   174  	// bits 0-4 indicate register, bits 5-7 indicate shift amount, bit 8 equals to 0.
   175  	case REG_LSL <= r && r < (REG_LSL+1<<8):
   176  		return fmt.Sprintf("R%d<<%d", r&31, (r>>5)&7)
   177  	case REG_ARNG <= r && r < REG_ELEM:
   178  		return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
   179  	case REG_ELEM <= r && r < REG_ZARNG:
   180  		return fmt.Sprintf("V%d.%s", r&31, arrange((r>>5)&15))
   181  	case REG_ZARNG <= r && r < REG_PZELEM:
   182  		return fmt.Sprintf("Z%d.%s", r&31, arrange((r>>5)&15))
   183  	case REG_PZELEM <= r && r < REG_PARNGZM:
   184  		regPrefix := "Z"
   185  		reg := r & 31
   186  		if r&(1<<5) != 0 {
   187  			regPrefix = "P"
   188  			if reg >= 16 {
   189  				regPrefix = "PN"
   190  				reg -= 16
   191  			}
   192  		}
   193  		return fmt.Sprintf("%s%d", regPrefix, reg)
   194  	case REG_PARNGZM <= r && r < REG_PARNGZM_END:
   195  		// SVE predicate register with arrangement.
   196  		// Pn.<T> or Pn/M, Pn/Z.
   197  		arng := (r >> 5) & 15
   198  		suffix := arrange(arng)
   199  		reg := r & 31
   200  		if reg >= 16 {
   201  			// PN registers
   202  			return fmt.Sprintf("PN%d.%s", reg-16, suffix)
   203  		}
   204  		return fmt.Sprintf("P%d.%s", reg, suffix)
   205  	}
   206  	// Return system register name.
   207  	name, _, _ := SysRegEnc(int16(r))
   208  	if name != "" {
   209  		return name
   210  	}
   211  	return fmt.Sprintf("badreg(%d)", r)
   212  }
   213  
   214  func DRconv(a int) string {
   215  	if a >= C_NONE && a <= C_NCLASS {
   216  		return cnames7[a]
   217  	}
   218  	return "C_??"
   219  }
   220  
   221  func SPCconv(a int64) string {
   222  	spc := SpecialOperand(a)
   223  	if spc >= SPOP_BEGIN && spc < SPOP_END {
   224  		return fmt.Sprintf("%s", spc)
   225  	}
   226  	return "SPC_??"
   227  }
   228  
   229  func rlconv(list int64) string {
   230  	str := ""
   231  
   232  	// For SIMD&FP register list in ARM64, the conv
   233  	// follows the ARM64 instruction decode schema
   234  	// | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... |
   235  	// +----+----+-----+---------+---------+-----+
   236  	// |    | Q  | ... | opcode  |   size  | ... |
   237  
   238  	// For Scalable Vector register lists, the conv
   239  	// follows:
   240  	// | 33 - 32 | 31 - 30 | ... | 15 - 12 | 11 - 10 | ... | 5 - 0 |
   241  	// +----+----+----+----+-----+---------+---------+-----+-------+
   242  	// |regprefix| class 1 | ... | reg cnt | class 2 | ... |  reg  |
   243  
   244  	firstReg := int(list & 31)
   245  	opcode := (list >> 12) & 15
   246  	var regCnt int
   247  	var t string
   248  	switch opcode {
   249  	case 0x7:
   250  		regCnt = 1
   251  	case 0xa:
   252  		regCnt = 2
   253  	case 0x6:
   254  		regCnt = 3
   255  	case 0x2:
   256  		regCnt = 4
   257  	case 0x1:
   258  		// 5 is the specifier for register range list, size is 1 register
   259  		regCnt = 5
   260  	case 0x3:
   261  		// 6 is the specifier for register range list, size is 4 register
   262  		regCnt = 6
   263  	default:
   264  		regCnt = -1
   265  	}
   266  	// Q:size
   267  	var regPrefix string
   268  	regType := (list >> 32) & 3
   269  	switch regType {
   270  	case 0:
   271  		regPrefix = "V"
   272  	case 1:
   273  		regPrefix = "Z"
   274  	case 2:
   275  		regPrefix = "P"
   276  	}
   277  	arng := ((list>>30)&3)<<2 | (list>>10)&3
   278  	switch arng {
   279  	case 0:
   280  		t = "B8"
   281  	case 4:
   282  		t = "B16"
   283  	case 1:
   284  		t = "H4"
   285  	case 5:
   286  		t = "H8"
   287  	case 2:
   288  		t = "S2"
   289  	case 6:
   290  		t = "S4"
   291  	case 3:
   292  		t = "D1"
   293  	case 7:
   294  		t = "D2"
   295  	case 9:
   296  		t = "B"
   297  	case 10:
   298  		t = "H"
   299  	case 11:
   300  		t = "S"
   301  	case 13:
   302  		t = "D"
   303  	case 14:
   304  		t = "Q"
   305  	}
   306  	if regCnt > 4 {
   307  		rangeSize := 2 << (regCnt - 5)
   308  		str = fmt.Sprintf("[%s%d.%s-%s%d.%s]", regPrefix, firstReg, t, regPrefix, (firstReg+rangeSize-1)&31, t)
   309  	} else {
   310  		for i := 0; i < regCnt; i++ {
   311  			if str == "" {
   312  				str += "["
   313  			} else {
   314  				str += ","
   315  			}
   316  			str += fmt.Sprintf("%s%d.", regPrefix, (firstReg+i)&31)
   317  			str += t
   318  		}
   319  		str += "]"
   320  	}
   321  	return str
   322  }
   323  
   324  func regname(r int) string {
   325  	if r&31 == 31 {
   326  		return "ZR"
   327  	}
   328  	return fmt.Sprintf("R%d", r&31)
   329  }
   330
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