cpu.go

Documentation: cmd/internal/obj/riscv

     1  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     2  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     3  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     4  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     5  //	Portions Copyright © 2004,2006 Bruce Ellis
     6  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     7  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
     8  //	Portions Copyright © 2009 The Go Authors.  All rights reserved.
     9  //	Portions Copyright © 2019 The Go Authors.  All rights reserved.
    10  //
    11  // Permission is hereby granted, free of charge, to any person obtaining a copy
    12  // of this software and associated documentation files (the "Software"), to deal
    13  // in the Software without restriction, including without limitation the rights
    14  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    15  // copies of the Software, and to permit persons to whom the Software is
    16  // furnished to do so, subject to the following conditions:
    17  //
    18  // The above copyright notice and this permission notice shall be included in
    19  // all copies or substantial portions of the Software.
    20  //
    21  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    22  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    23  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    24  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    25  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    26  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    27  // THE SOFTWARE.
    28  
    29  package riscv
    30  
    31  import (
    32  	"errors"
    33  	"fmt"
    34  
    35  	"cmd/internal/obj"
    36  )
    37  
    38  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
    39  
    40  const (
    41  	// Base register numberings.
    42  	REG_X0 = obj.RBaseRISCV + iota
    43  	REG_X1
    44  	REG_X2
    45  	REG_X3
    46  	REG_X4
    47  	REG_X5
    48  	REG_X6
    49  	REG_X7
    50  	REG_X8
    51  	REG_X9
    52  	REG_X10
    53  	REG_X11
    54  	REG_X12
    55  	REG_X13
    56  	REG_X14
    57  	REG_X15
    58  	REG_X16
    59  	REG_X17
    60  	REG_X18
    61  	REG_X19
    62  	REG_X20
    63  	REG_X21
    64  	REG_X22
    65  	REG_X23
    66  	REG_X24
    67  	REG_X25
    68  	REG_X26
    69  	REG_X27
    70  	REG_X28
    71  	REG_X29
    72  	REG_X30
    73  	REG_X31
    74  
    75  	// FP register numberings.
    76  	REG_F0
    77  	REG_F1
    78  	REG_F2
    79  	REG_F3
    80  	REG_F4
    81  	REG_F5
    82  	REG_F6
    83  	REG_F7
    84  	REG_F8
    85  	REG_F9
    86  	REG_F10
    87  	REG_F11
    88  	REG_F12
    89  	REG_F13
    90  	REG_F14
    91  	REG_F15
    92  	REG_F16
    93  	REG_F17
    94  	REG_F18
    95  	REG_F19
    96  	REG_F20
    97  	REG_F21
    98  	REG_F22
    99  	REG_F23
   100  	REG_F24
   101  	REG_F25
   102  	REG_F26
   103  	REG_F27
   104  	REG_F28
   105  	REG_F29
   106  	REG_F30
   107  	REG_F31
   108  
   109  	// This marks the end of the register numbering.
   110  	REG_END
   111  
   112  	// General registers reassigned to ABI names.
   113  	REG_ZERO = REG_X0
   114  	REG_RA   = REG_X1 // aka REG_LR
   115  	REG_SP   = REG_X2
   116  	REG_GP   = REG_X3 // aka REG_SB
   117  	REG_TP   = REG_X4
   118  	REG_T0   = REG_X5
   119  	REG_T1   = REG_X6
   120  	REG_T2   = REG_X7
   121  	REG_S0   = REG_X8
   122  	REG_S1   = REG_X9
   123  	REG_A0   = REG_X10
   124  	REG_A1   = REG_X11
   125  	REG_A2   = REG_X12
   126  	REG_A3   = REG_X13
   127  	REG_A4   = REG_X14
   128  	REG_A5   = REG_X15
   129  	REG_A6   = REG_X16
   130  	REG_A7   = REG_X17
   131  	REG_S2   = REG_X18
   132  	REG_S3   = REG_X19
   133  	REG_S4   = REG_X20
   134  	REG_S5   = REG_X21
   135  	REG_S6   = REG_X22
   136  	REG_S7   = REG_X23
   137  	REG_S8   = REG_X24
   138  	REG_S9   = REG_X25
   139  	REG_S10  = REG_X26 // aka REG_CTXT
   140  	REG_S11  = REG_X27 // aka REG_G
   141  	REG_T3   = REG_X28
   142  	REG_T4   = REG_X29
   143  	REG_T5   = REG_X30
   144  	REG_T6   = REG_X31 // aka REG_TMP
   145  
   146  	// Go runtime register names.
   147  	REG_CTXT = REG_S10 // Context for closures.
   148  	REG_G    = REG_S11 // G pointer.
   149  	REG_LR   = REG_RA  // Link register.
   150  	REG_TMP  = REG_T6  // Reserved for assembler use.
   151  
   152  	// ABI names for floating point registers.
   153  	REG_FT0  = REG_F0
   154  	REG_FT1  = REG_F1
   155  	REG_FT2  = REG_F2
   156  	REG_FT3  = REG_F3
   157  	REG_FT4  = REG_F4
   158  	REG_FT5  = REG_F5
   159  	REG_FT6  = REG_F6
   160  	REG_FT7  = REG_F7
   161  	REG_FS0  = REG_F8
   162  	REG_FS1  = REG_F9
   163  	REG_FA0  = REG_F10
   164  	REG_FA1  = REG_F11
   165  	REG_FA2  = REG_F12
   166  	REG_FA3  = REG_F13
   167  	REG_FA4  = REG_F14
   168  	REG_FA5  = REG_F15
   169  	REG_FA6  = REG_F16
   170  	REG_FA7  = REG_F17
   171  	REG_FS2  = REG_F18
   172  	REG_FS3  = REG_F19
   173  	REG_FS4  = REG_F20
   174  	REG_FS5  = REG_F21
   175  	REG_FS6  = REG_F22
   176  	REG_FS7  = REG_F23
   177  	REG_FS8  = REG_F24
   178  	REG_FS9  = REG_F25
   179  	REG_FS10 = REG_F26
   180  	REG_FS11 = REG_F27
   181  	REG_FT8  = REG_F28
   182  	REG_FT9  = REG_F29
   183  	REG_FT10 = REG_F30
   184  	REG_FT11 = REG_F31
   185  
   186  	// Names generated by the SSA compiler.
   187  	REGSP = REG_SP
   188  	REGG  = REG_G
   189  )
   190  
   191  // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
   192  var RISCV64DWARFRegisters = map[int16]int16{
   193  	// Integer Registers.
   194  	REG_X0:  0,
   195  	REG_X1:  1,
   196  	REG_X2:  2,
   197  	REG_X3:  3,
   198  	REG_X4:  4,
   199  	REG_X5:  5,
   200  	REG_X6:  6,
   201  	REG_X7:  7,
   202  	REG_X8:  8,
   203  	REG_X9:  9,
   204  	REG_X10: 10,
   205  	REG_X11: 11,
   206  	REG_X12: 12,
   207  	REG_X13: 13,
   208  	REG_X14: 14,
   209  	REG_X15: 15,
   210  	REG_X16: 16,
   211  	REG_X17: 17,
   212  	REG_X18: 18,
   213  	REG_X19: 19,
   214  	REG_X20: 20,
   215  	REG_X21: 21,
   216  	REG_X22: 22,
   217  	REG_X23: 23,
   218  	REG_X24: 24,
   219  	REG_X25: 25,
   220  	REG_X26: 26,
   221  	REG_X27: 27,
   222  	REG_X28: 28,
   223  	REG_X29: 29,
   224  	REG_X30: 30,
   225  	REG_X31: 31,
   226  
   227  	// Floating-Point Registers.
   228  	REG_F0:  32,
   229  	REG_F1:  33,
   230  	REG_F2:  34,
   231  	REG_F3:  35,
   232  	REG_F4:  36,
   233  	REG_F5:  37,
   234  	REG_F6:  38,
   235  	REG_F7:  39,
   236  	REG_F8:  40,
   237  	REG_F9:  41,
   238  	REG_F10: 42,
   239  	REG_F11: 43,
   240  	REG_F12: 44,
   241  	REG_F13: 45,
   242  	REG_F14: 46,
   243  	REG_F15: 47,
   244  	REG_F16: 48,
   245  	REG_F17: 49,
   246  	REG_F18: 50,
   247  	REG_F19: 51,
   248  	REG_F20: 52,
   249  	REG_F21: 53,
   250  	REG_F22: 54,
   251  	REG_F23: 55,
   252  	REG_F24: 56,
   253  	REG_F25: 57,
   254  	REG_F26: 58,
   255  	REG_F27: 59,
   256  	REG_F28: 60,
   257  	REG_F29: 61,
   258  	REG_F30: 62,
   259  	REG_F31: 63,
   260  }
   261  
   262  // Prog.Mark flags.
   263  const (
   264  	// USES_REG_TMP indicates that a machine instruction generated from the
   265  	// corresponding *obj.Prog uses the temporary register.
   266  	USES_REG_TMP = 1 << iota
   267  
   268  	// NEED_JAL_RELOC is set on JAL instructions to indicate that a
   269  	// R_RISCV_JAL relocation is needed.
   270  	NEED_JAL_RELOC
   271  
   272  	// NEED_CALL_RELOC is set on an AUIPC instruction to indicate that it
   273  	// is the first instruction in an AUIPC + JAL pair that needs a
   274  	// R_RISCV_CALL relocation.
   275  	NEED_CALL_RELOC
   276  
   277  	// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
   278  	// it is the first instruction in an AUIPC + I-type pair that needs a
   279  	// R_RISCV_PCREL_ITYPE relocation.
   280  	NEED_PCREL_ITYPE_RELOC
   281  
   282  	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
   283  	// it is the first instruction in an AUIPC + S-type pair that needs a
   284  	// R_RISCV_PCREL_STYPE relocation.
   285  	NEED_PCREL_STYPE_RELOC
   286  )
   287  
   288  // RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
   289  // at https://github.com/riscv/riscv-opcodes.
   290  //
   291  // As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
   292  //
   293  // See also "The RISC-V Instruction Set Manual" at https://riscv.org/specifications/.
   294  //
   295  // If you modify this table, you MUST run 'go generate' to regenerate anames.go!
   296  const (
   297  	// Unprivileged ISA (Document Version 20190608-Base-Ratified)
   298  
   299  	// 2.4: Integer Computational Instructions
   300  	AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
   301  	ASLTI
   302  	ASLTIU
   303  	AANDI
   304  	AORI
   305  	AXORI
   306  	ASLLI
   307  	ASRLI
   308  	ASRAI
   309  	ALUI
   310  	AAUIPC
   311  	AADD
   312  	ASLT
   313  	ASLTU
   314  	AAND
   315  	AOR
   316  	AXOR
   317  	ASLL
   318  	ASRL
   319  	ASUB
   320  	ASRA
   321  
   322  	// 2.5: Control Transfer Instructions
   323  	AJAL
   324  	AJALR
   325  	ABEQ
   326  	ABNE
   327  	ABLT
   328  	ABLTU
   329  	ABGE
   330  	ABGEU
   331  
   332  	// 2.6: Load and Store Instructions
   333  	ALW
   334  	ALWU
   335  	ALH
   336  	ALHU
   337  	ALB
   338  	ALBU
   339  	ASW
   340  	ASH
   341  	ASB
   342  
   343  	// 2.7: Memory Ordering Instructions
   344  	AFENCE
   345  	AFENCETSO
   346  	APAUSE
   347  
   348  	// 5.2: Integer Computational Instructions (RV64I)
   349  	AADDIW
   350  	ASLLIW
   351  	ASRLIW
   352  	ASRAIW
   353  	AADDW
   354  	ASLLW
   355  	ASRLW
   356  	ASUBW
   357  	ASRAW
   358  
   359  	// 5.3: Load and Store Instructions (RV64I)
   360  	ALD
   361  	ASD
   362  
   363  	// 7.1: Multiplication Operations
   364  	AMUL
   365  	AMULH
   366  	AMULHU
   367  	AMULHSU
   368  	AMULW
   369  	ADIV
   370  	ADIVU
   371  	AREM
   372  	AREMU
   373  	ADIVW
   374  	ADIVUW
   375  	AREMW
   376  	AREMUW
   377  
   378  	// 8.2: Load-Reserved/Store-Conditional Instructions
   379  	ALRD
   380  	ASCD
   381  	ALRW
   382  	ASCW
   383  
   384  	// 8.3: Atomic Memory Operations
   385  	AAMOSWAPD
   386  	AAMOADDD
   387  	AAMOANDD
   388  	AAMOORD
   389  	AAMOXORD
   390  	AAMOMAXD
   391  	AAMOMAXUD
   392  	AAMOMIND
   393  	AAMOMINUD
   394  	AAMOSWAPW
   395  	AAMOADDW
   396  	AAMOANDW
   397  	AAMOORW
   398  	AAMOXORW
   399  	AAMOMAXW
   400  	AAMOMAXUW
   401  	AAMOMINW
   402  	AAMOMINUW
   403  
   404  	// 10.1: Base Counters and Timers
   405  	ARDCYCLE
   406  	ARDCYCLEH
   407  	ARDTIME
   408  	ARDTIMEH
   409  	ARDINSTRET
   410  	ARDINSTRETH
   411  
   412  	// 11.2: Floating-Point Control and Status Register
   413  	AFRCSR
   414  	AFSCSR
   415  	AFRRM
   416  	AFSRM
   417  	AFRFLAGS
   418  	AFSFLAGS
   419  	AFSRMI
   420  	AFSFLAGSI
   421  
   422  	// 11.5: Single-Precision Load and Store Instructions
   423  	AFLW
   424  	AFSW
   425  
   426  	// 11.6: Single-Precision Floating-Point Computational Instructions
   427  	AFADDS
   428  	AFSUBS
   429  	AFMULS
   430  	AFDIVS
   431  	AFMINS
   432  	AFMAXS
   433  	AFSQRTS
   434  	AFMADDS
   435  	AFMSUBS
   436  	AFNMADDS
   437  	AFNMSUBS
   438  
   439  	// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
   440  	AFCVTWS
   441  	AFCVTLS
   442  	AFCVTSW
   443  	AFCVTSL
   444  	AFCVTWUS
   445  	AFCVTLUS
   446  	AFCVTSWU
   447  	AFCVTSLU
   448  	AFSGNJS
   449  	AFSGNJNS
   450  	AFSGNJXS
   451  	AFMVXS
   452  	AFMVSX
   453  	AFMVXW
   454  	AFMVWX
   455  
   456  	// 11.8: Single-Precision Floating-Point Compare Instructions
   457  	AFEQS
   458  	AFLTS
   459  	AFLES
   460  
   461  	// 11.9: Single-Precision Floating-Point Classify Instruction
   462  	AFCLASSS
   463  
   464  	// 12.3: Double-Precision Load and Store Instructions
   465  	AFLD
   466  	AFSD
   467  
   468  	// 12.4: Double-Precision Floating-Point Computational Instructions
   469  	AFADDD
   470  	AFSUBD
   471  	AFMULD
   472  	AFDIVD
   473  	AFMIND
   474  	AFMAXD
   475  	AFSQRTD
   476  	AFMADDD
   477  	AFMSUBD
   478  	AFNMADDD
   479  	AFNMSUBD
   480  
   481  	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
   482  	AFCVTWD
   483  	AFCVTLD
   484  	AFCVTDW
   485  	AFCVTDL
   486  	AFCVTWUD
   487  	AFCVTLUD
   488  	AFCVTDWU
   489  	AFCVTDLU
   490  	AFCVTSD
   491  	AFCVTDS
   492  	AFSGNJD
   493  	AFSGNJND
   494  	AFSGNJXD
   495  	AFMVXD
   496  	AFMVDX
   497  
   498  	// 12.6: Double-Precision Floating-Point Compare Instructions
   499  	AFEQD
   500  	AFLTD
   501  	AFLED
   502  
   503  	// 12.7: Double-Precision Floating-Point Classify Instruction
   504  	AFCLASSD
   505  
   506  	// 13.1 Quad-Precision Load and Store Instructions
   507  	AFLQ
   508  	AFSQ
   509  
   510  	// 13.2: Quad-Precision Computational Instructions
   511  	AFADDQ
   512  	AFSUBQ
   513  	AFMULQ
   514  	AFDIVQ
   515  	AFMINQ
   516  	AFMAXQ
   517  	AFSQRTQ
   518  	AFMADDQ
   519  	AFMSUBQ
   520  	AFNMADDQ
   521  	AFNMSUBQ
   522  
   523  	// 13.3 Quad-Precision Convert and Move Instructions
   524  	AFCVTWQ
   525  	AFCVTLQ
   526  	AFCVTSQ
   527  	AFCVTDQ
   528  	AFCVTQW
   529  	AFCVTQL
   530  	AFCVTQS
   531  	AFCVTQD
   532  	AFCVTWUQ
   533  	AFCVTLUQ
   534  	AFCVTQWU
   535  	AFCVTQLU
   536  	AFSGNJQ
   537  	AFSGNJNQ
   538  	AFSGNJXQ
   539  
   540  	// 13.4 Quad-Precision Floating-Point Compare Instructions
   541  	AFEQQ
   542  	AFLEQ
   543  	AFLTQ
   544  
   545  	// 13.5 Quad-Precision Floating-Point Classify Instruction
   546  	AFCLASSQ
   547  
   548  	// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
   549  
   550  	// 3.1.9: Instructions to Access CSRs
   551  	ACSRRW
   552  	ACSRRS
   553  	ACSRRC
   554  	ACSRRWI
   555  	ACSRRSI
   556  	ACSRRCI
   557  
   558  	// 3.2.1: Environment Call and Breakpoint
   559  	AECALL
   560  	ASCALL
   561  	AEBREAK
   562  	ASBREAK
   563  
   564  	// 3.2.2: Trap-Return Instructions
   565  	AMRET
   566  	ASRET
   567  	ADRET
   568  
   569  	// 3.2.3: Wait for Interrupt
   570  	AWFI
   571  
   572  	// 4.2.1: Supervisor Memory-Management Fence Instruction
   573  	ASFENCEVMA
   574  
   575  	//
   576  	// RISC-V Bit-Manipulation ISA-extensions (1.0)
   577  	//
   578  
   579  	// 1.1: Address Generation Instructions (Zba)
   580  	AADDUW
   581  	ASH1ADD
   582  	ASH1ADDUW
   583  	ASH2ADD
   584  	ASH2ADDUW
   585  	ASH3ADD
   586  	ASH3ADDUW
   587  	ASLLIUW
   588  
   589  	// 1.2: Basic Bit Manipulation (Zbb)
   590  	AANDN
   591  	AORN
   592  	AXNOR
   593  	ACLZ
   594  	ACLZW
   595  	ACTZ
   596  	ACTZW
   597  	ACPOP
   598  	ACPOPW
   599  	AMAX
   600  	AMAXU
   601  	AMIN
   602  	AMINU
   603  	ASEXTB
   604  	ASEXTH
   605  	AZEXTH
   606  
   607  	// 1.3: Bitwise Rotation (Zbb)
   608  	AROL
   609  	AROLW
   610  	AROR
   611  	ARORI
   612  	ARORIW
   613  	ARORW
   614  	AORCB
   615  	AREV8
   616  
   617  	// 1.5: Single-bit Instructions (Zbs)
   618  	ABCLR
   619  	ABCLRI
   620  	ABEXT
   621  	ABEXTI
   622  	ABINV
   623  	ABINVI
   624  	ABSET
   625  	ABSETI
   626  
   627  	// The escape hatch. Inserts a single 32-bit word.
   628  	AWORD
   629  
   630  	// Pseudo-instructions.  These get translated by the assembler into other
   631  	// instructions, based on their operands.
   632  	ABEQZ
   633  	ABGEZ
   634  	ABGT
   635  	ABGTU
   636  	ABGTZ
   637  	ABLE
   638  	ABLEU
   639  	ABLEZ
   640  	ABLTZ
   641  	ABNEZ
   642  	AFABSD
   643  	AFABSS
   644  	AFNEGD
   645  	AFNEGS
   646  	AFNED
   647  	AFNES
   648  	AMOV
   649  	AMOVB
   650  	AMOVBU
   651  	AMOVF
   652  	AMOVD
   653  	AMOVH
   654  	AMOVHU
   655  	AMOVW
   656  	AMOVWU
   657  	ANEG
   658  	ANEGW
   659  	ANOT
   660  	ASEQZ
   661  	ASNEZ
   662  
   663  	// End marker
   664  	ALAST
   665  )
   666  
   667  // opSuffix encoding to uint8 which fit into p.Scond
   668  var rmSuffixSet = map[string]uint8{
   669  	"RNE": RM_RNE,
   670  	"RTZ": RM_RTZ,
   671  	"RDN": RM_RDN,
   672  	"RUP": RM_RUP,
   673  	"RMM": RM_RMM,
   674  }
   675  
   676  const rmSuffixBit uint8 = 1 << 7
   677  
   678  func rmSuffixEncode(s string) (uint8, error) {
   679  	if s == "" {
   680  		return 0, errors.New("empty suffix")
   681  	}
   682  	enc, ok := rmSuffixSet[s]
   683  	if !ok {
   684  		return 0, fmt.Errorf("invalid encoding for unknown suffix:%q", s)
   685  	}
   686  	return enc | rmSuffixBit, nil
   687  }
   688  
   689  func rmSuffixString(u uint8) (string, error) {
   690  	if u&rmSuffixBit == 0 {
   691  		return "", fmt.Errorf("invalid suffix, require round mode bit:%x", u)
   692  	}
   693  
   694  	u &^= rmSuffixBit
   695  	for k, v := range rmSuffixSet {
   696  		if v == u {
   697  			return k, nil
   698  		}
   699  	}
   700  	return "", fmt.Errorf("unknown suffix:%x", u)
   701  }
   702  
   703  const (
   704  	RM_RNE uint8 = iota // Round to Nearest, ties to Even
   705  	RM_RTZ              // Round towards Zero
   706  	RM_RDN              // Round Down
   707  	RM_RUP              // Round Up
   708  	RM_RMM              // Round to Nearest, ties to Max Magnitude
   709  )
   710  
   711  // All unary instructions which write to their arguments (as opposed to reading
   712  // from them) go here. The assembly parser uses this information to populate
   713  // its AST in a semantically reasonable way.
   714  //
   715  // Any instructions not listed here are assumed to either be non-unary or to read
   716  // from its argument.
   717  var unaryDst = map[obj.As]bool{
   718  	ARDCYCLE:    true,
   719  	ARDCYCLEH:   true,
   720  	ARDTIME:     true,
   721  	ARDTIMEH:    true,
   722  	ARDINSTRET:  true,
   723  	ARDINSTRETH: true,
   724  }
   725  
   726  // Instruction encoding masks.
   727  const (
   728  	// BTypeImmMask is a mask including only the immediate portion of
   729  	// B-type instructions.
   730  	BTypeImmMask = 0xfe000f80
   731  
   732  	// CBTypeImmMask is a mask including only the immediate portion of
   733  	// CB-type instructions.
   734  	CBTypeImmMask = 0x1c7c
   735  
   736  	// CJTypeImmMask is a mask including only the immediate portion of
   737  	// CJ-type instructions.
   738  	CJTypeImmMask = 0x1f7c
   739  
   740  	// ITypeImmMask is a mask including only the immediate portion of
   741  	// I-type instructions.
   742  	ITypeImmMask = 0xfff00000
   743  
   744  	// JTypeImmMask is a mask including only the immediate portion of
   745  	// J-type instructions.
   746  	JTypeImmMask = 0xfffff000
   747  
   748  	// STypeImmMask is a mask including only the immediate portion of
   749  	// S-type instructions.
   750  	STypeImmMask = 0xfe000f80
   751  
   752  	// UTypeImmMask is a mask including only the immediate portion of
   753  	// U-type instructions.
   754  	UTypeImmMask = 0xfffff000
   755  )
   756
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