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30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "slices"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 62, as: AMLGR, a1: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
179 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
181 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
183 {i: 47, as: ANEG, a6: C_REG},
184
185
186 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
187 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
188 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
190 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
192 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
193 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
195 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
199 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
200 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
201
202
203 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
204
205
206 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
208 {i: 33, as: AFABS, a6: C_FREG},
209 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
210 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
212 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
213 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
215 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
216 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
217 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
218 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
219 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
220 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
221 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
222 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
223 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
224 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
225 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
226
227
228 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
229 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
230 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
231 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
232
233
234 {i: 5, as: ASYSCALL},
235 {i: 77, as: ASYSCALL, a1: C_SCON},
236
237
238 {i: 16, as: ABEQ, a6: C_SBRA},
239 {i: 16, as: ABRC, a1: C_SCON, a6: C_SBRA},
240 {i: 11, as: ABR, a6: C_LBRA},
241 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
242 {i: 18, as: ABR, a6: C_REG},
243 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
244 {i: 15, as: ABR, a6: C_ZOREG},
245 {i: 15, as: ABC, a6: C_ZOREG},
246
247
248 {i: 89, as: ACGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
249 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
250 {i: 89, as: ACLGRJ, a1: C_SCON, a2: C_REG, a3: C_REG, a6: C_SBRA},
251 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
252 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
253 {i: 90, as: ACGIJ, a1: C_SCON, a2: C_REG, a3: C_SCON, a6: C_SBRA},
254 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
255 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
256 {i: 90, as: ACLGIJ, a1: C_SCON, a2: C_REG, a3: C_ADDCON, a6: C_SBRA},
257 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
258
259
260 {i: 41, as: ABRCT, a1: C_REG, a6: C_SBRA},
261 {i: 41, as: ABRCTG, a1: C_REG, a6: C_SBRA},
262
263
264 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
265
266
267 {i: 25, as: ALOCGR, a1: C_SCON, a2: C_REG, a6: C_REG},
268
269
270 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
271
272
273 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
274
275
276 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
277 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
278 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
279 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
280 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
281 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
282
283
284 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
285
286
287 {i: 92, as: AIPM, a1: C_REG},
288
289
290 {i: 76, as: ASPM, a1: C_REG},
291
292
293 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
294 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
295 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
296 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
297
298
299 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
300 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
301
302
303 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
304 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
305 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
306 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
307
308
309 {i: 40, as: ABYTE, a1: C_SCON},
310 {i: 40, as: AWORD, a1: C_LCON},
311 {i: 31, as: ADWORD, a1: C_LCON},
312 {i: 31, as: ADWORD, a1: C_DCON},
313
314
315 {i: 80, as: ASYNC},
316
317
318 {i: 88, as: ASTCK, a6: C_SAUTO},
319 {i: 88, as: ASTCK, a6: C_SOREG},
320
321
322 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
323 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
324 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
325
326
327 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
328 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
329 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
330 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
331 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
332
333
334 {i: 78, as: obj.AUNDEF},
335
336
337 {i: 73, as: ABRRK},
338
339
340 {i: 66, as: ANOPH},
341
342
343
344
345 {i: 124, as: AKM, a1: C_REG, a6: C_REG},
346
347
348 {i: 125, as: AKDSA, a1: C_REG, a6: C_REG},
349
350
351 {i: 126, as: AKMA, a1: C_REG, a2: C_REG, a6: C_REG},
352
353
354
355
356 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
357 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
358 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
359 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
363 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
364 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
365 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
366
367
368 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
369 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
370
371
372 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
373 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
374
375
376 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
377 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
378 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
379 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
380 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
381 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
382 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
383 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
384
385
386 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
387 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
388
389
390 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
391 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
392
393
394 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
395 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
396
397
398 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
399 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
400
401
402 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
403 {i: 109, as: AVZERO, a6: C_VREG},
404 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
405 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
406 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
407 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
408
409
410 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
411
412
413 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
414
415
416
417 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
418 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
419
420
421 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
422
423
424 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
425
426
427 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
428
429
430 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
431 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
432 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
433
434
435 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
436 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
437 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
438 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
439
440
441 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
442 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
443
444
445 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
446
447
448 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
449
450
451 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
452 }
453
454 var oprange [ALAST & obj.AMask][]Optab
455
456 var xcmp [C_NCLASS][C_NCLASS]bool
457
458 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
459 if ctxt.Retpoline {
460 ctxt.Diag("-spectre=ret not supported on s390x")
461 ctxt.Retpoline = false
462 }
463
464 p := cursym.Func().Text
465 if p == nil || p.Link == nil {
466 return
467 }
468
469 if oprange[AORW&obj.AMask] == nil {
470 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
471 }
472
473 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
474
475 buffer := make([]byte, 0)
476 changed := true
477 loop := 0
478 nrelocs0 := len(c.cursym.R)
479 for changed {
480 if loop > 100 {
481 c.ctxt.Diag("stuck in spanz loop")
482 break
483 }
484 changed = false
485 buffer = buffer[:0]
486 for i := range c.cursym.R[nrelocs0:] {
487 c.cursym.R[nrelocs0+i] = obj.Reloc{}
488 }
489 c.cursym.R = c.cursym.R[:nrelocs0]
490 for p := c.cursym.Func().Text; p != nil; p = p.Link {
491 pc := int64(len(buffer))
492 if pc != p.Pc {
493 changed = true
494 }
495 p.Pc = pc
496 c.pc = p.Pc
497 c.asmout(p, &buffer)
498 if pc == int64(len(buffer)) {
499 switch p.As {
500 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
501
502 default:
503 c.ctxt.Diag("zero-width instruction\n%v", p)
504 }
505 }
506 }
507 loop++
508 }
509
510 c.cursym.Size = int64(len(buffer))
511 if c.cursym.Size%funcAlign != 0 {
512 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
513 }
514 c.cursym.Grow(c.cursym.Size)
515 copy(c.cursym.P, buffer)
516
517
518
519
520
521 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, nil)
522 }
523
524
525 func (c *ctxtz) isUnsafePoint(p *obj.Prog) bool {
526 if p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP {
527 return true
528 }
529 for _, a := range p.RestArgs {
530 if a.Reg == REGTMP {
531 return true
532 }
533 }
534 return p.Mark&USETMP != 0
535 }
536
537 func isint32(v int64) bool {
538 return int64(int32(v)) == v
539 }
540
541 func isuint32(v uint64) bool {
542 return uint64(uint32(v)) == v
543 }
544
545 func (c *ctxtz) aclass(a *obj.Addr) int {
546 switch a.Type {
547 case obj.TYPE_NONE:
548 return C_NONE
549
550 case obj.TYPE_REG:
551 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
552 return C_REG
553 }
554 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
555 return C_FREG
556 }
557 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
558 return C_AREG
559 }
560 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
561 return C_VREG
562 }
563 return C_GOK
564
565 case obj.TYPE_MEM:
566 switch a.Name {
567 case obj.NAME_EXTERN,
568 obj.NAME_STATIC:
569 if a.Sym == nil {
570
571 break
572 }
573 c.instoffset = a.Offset
574 if a.Sym.Type == objabi.STLSBSS {
575 if c.ctxt.Flag_shared {
576 return C_TLS_IE
577 }
578 return C_TLS_LE
579 }
580 return C_ADDR
581
582 case obj.NAME_GOTREF:
583 return C_GOTADDR
584
585 case obj.NAME_AUTO:
586 if a.Reg == REGSP {
587
588
589 a.Reg = obj.REG_NONE
590 }
591 c.instoffset = int64(c.autosize) + a.Offset
592 if c.instoffset >= -BIG && c.instoffset < BIG {
593 return C_SAUTO
594 }
595 return C_LAUTO
596
597 case obj.NAME_PARAM:
598 if a.Reg == REGSP {
599
600
601 a.Reg = obj.REG_NONE
602 }
603 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
604 if c.instoffset >= -BIG && c.instoffset < BIG {
605 return C_SAUTO
606 }
607 return C_LAUTO
608
609 case obj.NAME_NONE:
610 c.instoffset = a.Offset
611 if c.instoffset == 0 {
612 return C_ZOREG
613 }
614 if c.instoffset >= -BIG && c.instoffset < BIG {
615 return C_SOREG
616 }
617 return C_LOREG
618 }
619
620 return C_GOK
621
622 case obj.TYPE_TEXTSIZE:
623 return C_TEXTSIZE
624
625 case obj.TYPE_FCONST:
626 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
627 return C_ZCON
628 }
629 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
630
631 case obj.TYPE_CONST,
632 obj.TYPE_ADDR:
633 switch a.Name {
634 case obj.NAME_NONE:
635 c.instoffset = a.Offset
636 if a.Reg != 0 {
637 if -BIG <= c.instoffset && c.instoffset <= BIG {
638 return C_SACON
639 }
640 if isint32(c.instoffset) {
641 return C_LACON
642 }
643 return C_DACON
644 }
645
646 case obj.NAME_EXTERN,
647 obj.NAME_STATIC:
648 s := a.Sym
649 if s == nil {
650 return C_GOK
651 }
652 c.instoffset = a.Offset
653
654 return C_SYMADDR
655
656 case obj.NAME_AUTO:
657 if a.Reg == REGSP {
658
659
660 a.Reg = obj.REG_NONE
661 }
662 c.instoffset = int64(c.autosize) + a.Offset
663 if c.instoffset >= -BIG && c.instoffset < BIG {
664 return C_SACON
665 }
666 return C_LACON
667
668 case obj.NAME_PARAM:
669 if a.Reg == REGSP {
670
671
672 a.Reg = obj.REG_NONE
673 }
674 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
675 if c.instoffset >= -BIG && c.instoffset < BIG {
676 return C_SACON
677 }
678 return C_LACON
679
680 default:
681 return C_GOK
682 }
683
684 if c.instoffset == 0 {
685 return C_ZCON
686 }
687 if c.instoffset >= 0 {
688 if c.instoffset <= 0x7fff {
689 return C_SCON
690 }
691 if c.instoffset <= 0xffff {
692 return C_ANDCON
693 }
694 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
695 return C_UCON
696 }
697 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
698 return C_LCON
699 }
700 return C_DCON
701 }
702
703 if c.instoffset >= -0x8000 {
704 return C_ADDCON
705 }
706 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
707 return C_UCON
708 }
709 if isint32(c.instoffset) {
710 return C_LCON
711 }
712 return C_DCON
713
714 case obj.TYPE_BRANCH:
715 return C_SBRA
716 }
717
718 return C_GOK
719 }
720
721 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
722
723 if p.Optab != 0 {
724 return &optab[p.Optab-1]
725 }
726 if len(p.RestArgs) > 3 {
727 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
728 return nil
729 }
730
731
732 p.From.Class = int8(c.aclass(&p.From) + 1)
733 p.To.Class = int8(c.aclass(&p.To) + 1)
734 for i := range p.RestArgs {
735 p.RestArgs[i].Addr.Class = int8(c.aclass(&p.RestArgs[i].Addr) + 1)
736 }
737
738
739 args := [...]int8{
740 p.From.Class - 1,
741 C_NONE,
742 C_NONE,
743 C_NONE,
744 C_NONE,
745 p.To.Class - 1,
746 }
747
748 switch {
749 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
750 args[1] = C_REG
751 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
752 args[1] = C_VREG
753 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
754 args[1] = C_FREG
755 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
756 args[1] = C_AREG
757 }
758
759 for i, a := range p.RestArgs {
760 args[2+i] = a.Class - 1
761 }
762
763
764 ops := oprange[p.As&obj.AMask]
765 cmp := [len(args)]*[C_NCLASS]bool{}
766 for i := range cmp {
767 cmp[i] = &xcmp[args[i]]
768 }
769 for i := range ops {
770 op := &ops[i]
771 if cmp[0][op.a1] && cmp[1][op.a2] &&
772 cmp[2][op.a3] && cmp[3][op.a4] &&
773 cmp[4][op.a5] && cmp[5][op.a6] {
774 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
775 return op
776 }
777 }
778
779
780 s := ""
781 for _, a := range args {
782 s += fmt.Sprintf(" %v", DRconv(int(a)))
783 }
784 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
785 c.ctxt.Diag("prog: %v\n", p)
786 return nil
787 }
788
789 func cmp(a int, b int) bool {
790 if a == b {
791 return true
792 }
793 switch a {
794 case C_DCON:
795 if b == C_LCON {
796 return true
797 }
798 fallthrough
799 case C_LCON:
800 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
801 return true
802 }
803
804 case C_ADDCON:
805 if b == C_ZCON || b == C_SCON {
806 return true
807 }
808
809 case C_ANDCON:
810 if b == C_ZCON || b == C_SCON {
811 return true
812 }
813
814 case C_UCON:
815 if b == C_ZCON || b == C_SCON {
816 return true
817 }
818
819 case C_SCON:
820 if b == C_ZCON {
821 return true
822 }
823
824 case C_LACON:
825 if b == C_SACON {
826 return true
827 }
828
829 case C_LBRA:
830 if b == C_SBRA {
831 return true
832 }
833
834 case C_LAUTO:
835 if b == C_SAUTO {
836 return true
837 }
838
839 case C_LOREG:
840 if b == C_ZOREG || b == C_SOREG {
841 return true
842 }
843
844 case C_SOREG:
845 if b == C_ZOREG {
846 return true
847 }
848
849 case C_ANY:
850 return true
851 }
852
853 return false
854 }
855
856 func ocmp(p1, p2 Optab) int {
857 if p1.as != p2.as {
858 return int(p1.as) - int(p2.as)
859 }
860 if p1.a1 != p2.a1 {
861 return int(p1.a1) - int(p2.a1)
862 }
863 if p1.a2 != p2.a2 {
864 return int(p1.a2) - int(p2.a2)
865 }
866 if p1.a3 != p2.a3 {
867 return int(p1.a3) - int(p2.a3)
868 }
869 if p1.a4 != p2.a4 {
870 return int(p1.a4) - int(p2.a4)
871 }
872 return 0
873 }
874 func opset(a, b obj.As) {
875 oprange[a&obj.AMask] = oprange[b&obj.AMask]
876 }
877
878 func buildop(ctxt *obj.Link) {
879 if oprange[AORW&obj.AMask] != nil {
880
881
882
883 return
884 }
885
886 for i := 0; i < C_NCLASS; i++ {
887 for n := 0; n < C_NCLASS; n++ {
888 if cmp(n, i) {
889 xcmp[i][n] = true
890 }
891 }
892 }
893 slices.SortFunc(optab, ocmp)
894 for i := 0; i < len(optab); i++ {
895 r := optab[i].as
896 start := i
897 for ; i+1 < len(optab); i++ {
898 if optab[i+1].as != r {
899 break
900 }
901 }
902 oprange[r&obj.AMask] = optab[start : i+1]
903
904
905
906 switch r {
907 case AADD:
908 opset(AADDC, r)
909 opset(AADDW, r)
910 opset(AADDE, r)
911 opset(AMULLD, r)
912 opset(AMULLW, r)
913 case ADIVW:
914 opset(ADIVD, r)
915 opset(ADIVDU, r)
916 opset(ADIVWU, r)
917 opset(AMODD, r)
918 opset(AMODDU, r)
919 opset(AMODW, r)
920 opset(AMODWU, r)
921 case AMULHD:
922 opset(AMULHDU, r)
923 case AMOVBZ:
924 opset(AMOVH, r)
925 opset(AMOVHZ, r)
926 case ALA:
927 opset(ALAY, r)
928 case AMVC:
929 opset(AMVCIN, r)
930 opset(ACLC, r)
931 opset(AXC, r)
932 opset(AOC, r)
933 opset(ANC, r)
934 case ASTCK:
935 opset(ASTCKC, r)
936 opset(ASTCKE, r)
937 opset(ASTCKF, r)
938 case ALAAG:
939 opset(ALAA, r)
940 opset(ALAAL, r)
941 opset(ALAALG, r)
942 opset(ALAN, r)
943 opset(ALANG, r)
944 opset(ALAX, r)
945 opset(ALAXG, r)
946 opset(ALAO, r)
947 opset(ALAOG, r)
948 case ASTMG:
949 opset(ASTMY, r)
950 case ALMG:
951 opset(ALMY, r)
952 case ABEQ:
953 opset(ABGE, r)
954 opset(ABGT, r)
955 opset(ABLE, r)
956 opset(ABLT, r)
957 opset(ABNE, r)
958 opset(ABVC, r)
959 opset(ABVS, r)
960 opset(ABLEU, r)
961 opset(ABLTU, r)
962 case ABR:
963 opset(ABL, r)
964 case ABC:
965 opset(ABCL, r)
966 case AFABS:
967 opset(AFNABS, r)
968 opset(ALPDFR, r)
969 opset(ALNDFR, r)
970 opset(AFNEG, r)
971 opset(AFNEGS, r)
972 opset(ALCDBR, r)
973 opset(ALEDBR, r)
974 opset(ALDEBR, r)
975 opset(AFSQRT, r)
976 opset(AFSQRTS, r)
977 case AFADD:
978 opset(AFADDS, r)
979 opset(AFDIV, r)
980 opset(AFDIVS, r)
981 opset(AFSUB, r)
982 opset(AFSUBS, r)
983 case AFMADD:
984 opset(AFMADDS, r)
985 opset(AFMSUB, r)
986 opset(AFMSUBS, r)
987 case AFMUL:
988 opset(AFMULS, r)
989 case AFCMPO:
990 opset(AFCMPU, r)
991 opset(ACEBR, r)
992 case AAND:
993 opset(AOR, r)
994 opset(AXOR, r)
995 case AANDW:
996 opset(AORW, r)
997 opset(AXORW, r)
998 case ASLD:
999 opset(ASRD, r)
1000 opset(ASLW, r)
1001 opset(ASRW, r)
1002 opset(ASRAD, r)
1003 opset(ASRAW, r)
1004 opset(ARLL, r)
1005 opset(ARLLG, r)
1006 case ARNSBG:
1007 opset(ARXSBG, r)
1008 opset(AROSBG, r)
1009 opset(ARNSBGT, r)
1010 opset(ARXSBGT, r)
1011 opset(AROSBGT, r)
1012 opset(ARISBG, r)
1013 opset(ARISBGN, r)
1014 opset(ARISBGZ, r)
1015 opset(ARISBGNZ, r)
1016 opset(ARISBHG, r)
1017 opset(ARISBLG, r)
1018 opset(ARISBHGZ, r)
1019 opset(ARISBLGZ, r)
1020 case ACSG:
1021 opset(ACS, r)
1022 case ASUB:
1023 opset(ASUBC, r)
1024 opset(ASUBE, r)
1025 opset(ASUBW, r)
1026 case ANEG:
1027 opset(ANEGW, r)
1028 case AFMOVD:
1029 opset(AFMOVS, r)
1030 case AMOVDBR:
1031 opset(AMOVWBR, r)
1032 case ACMP:
1033 opset(ACMPW, r)
1034 case ACMPU:
1035 opset(ACMPWU, r)
1036 case ATMHH:
1037 opset(ATMHL, r)
1038 opset(ATMLH, r)
1039 opset(ATMLL, r)
1040 case ACEFBRA:
1041 opset(ACDFBRA, r)
1042 opset(ACEGBRA, r)
1043 opset(ACDGBRA, r)
1044 opset(ACELFBR, r)
1045 opset(ACDLFBR, r)
1046 opset(ACELGBR, r)
1047 opset(ACDLGBR, r)
1048 case ACFEBRA:
1049 opset(ACFDBRA, r)
1050 opset(ACGEBRA, r)
1051 opset(ACGDBRA, r)
1052 opset(ACLFEBR, r)
1053 opset(ACLFDBR, r)
1054 opset(ACLGEBR, r)
1055 opset(ACLGDBR, r)
1056 case AFIEBR:
1057 opset(AFIDBR, r)
1058 case ACMPBEQ:
1059 opset(ACMPBGE, r)
1060 opset(ACMPBGT, r)
1061 opset(ACMPBLE, r)
1062 opset(ACMPBLT, r)
1063 opset(ACMPBNE, r)
1064 case ACMPUBEQ:
1065 opset(ACMPUBGE, r)
1066 opset(ACMPUBGT, r)
1067 opset(ACMPUBLE, r)
1068 opset(ACMPUBLT, r)
1069 opset(ACMPUBNE, r)
1070 case ACGRJ:
1071 opset(ACRJ, r)
1072 case ACLGRJ:
1073 opset(ACLRJ, r)
1074 case ACGIJ:
1075 opset(ACIJ, r)
1076 case ACLGIJ:
1077 opset(ACLIJ, r)
1078 case AMOVDEQ:
1079 opset(AMOVDGE, r)
1080 opset(AMOVDGT, r)
1081 opset(AMOVDLE, r)
1082 opset(AMOVDLT, r)
1083 opset(AMOVDNE, r)
1084 case ALOCGR:
1085 opset(ALOCR, r)
1086 case ALTDBR:
1087 opset(ALTEBR, r)
1088 case ATCDB:
1089 opset(ATCEB, r)
1090 case AVL:
1091 opset(AVLLEZB, r)
1092 opset(AVLLEZH, r)
1093 opset(AVLLEZF, r)
1094 opset(AVLLEZG, r)
1095 opset(AVLREPB, r)
1096 opset(AVLREPH, r)
1097 opset(AVLREPF, r)
1098 opset(AVLREPG, r)
1099 case AVLEG:
1100 opset(AVLBB, r)
1101 opset(AVLEB, r)
1102 opset(AVLEH, r)
1103 opset(AVLEF, r)
1104 opset(AVLEG, r)
1105 opset(AVLREP, r)
1106 case AVSTEG:
1107 opset(AVSTEB, r)
1108 opset(AVSTEH, r)
1109 opset(AVSTEF, r)
1110 case AVSCEG:
1111 opset(AVSCEF, r)
1112 case AVGEG:
1113 opset(AVGEF, r)
1114 case AVESLG:
1115 opset(AVESLB, r)
1116 opset(AVESLH, r)
1117 opset(AVESLF, r)
1118 opset(AVERLLB, r)
1119 opset(AVERLLH, r)
1120 opset(AVERLLF, r)
1121 opset(AVERLLG, r)
1122 opset(AVESRAB, r)
1123 opset(AVESRAH, r)
1124 opset(AVESRAF, r)
1125 opset(AVESRAG, r)
1126 opset(AVESRLB, r)
1127 opset(AVESRLH, r)
1128 opset(AVESRLF, r)
1129 opset(AVESRLG, r)
1130 case AVLGVG:
1131 opset(AVLGVB, r)
1132 opset(AVLGVH, r)
1133 opset(AVLGVF, r)
1134 case AVLVGG:
1135 opset(AVLVGB, r)
1136 opset(AVLVGH, r)
1137 opset(AVLVGF, r)
1138 case AVZERO:
1139 opset(AVONE, r)
1140 case AVREPIG:
1141 opset(AVREPIB, r)
1142 opset(AVREPIH, r)
1143 opset(AVREPIF, r)
1144 case AVLEIG:
1145 opset(AVLEIB, r)
1146 opset(AVLEIH, r)
1147 opset(AVLEIF, r)
1148 case AVGMG:
1149 opset(AVGMB, r)
1150 opset(AVGMH, r)
1151 opset(AVGMF, r)
1152 case AVREPG:
1153 opset(AVREPB, r)
1154 opset(AVREPH, r)
1155 opset(AVREPF, r)
1156 case AVERIMG:
1157 opset(AVERIMB, r)
1158 opset(AVERIMH, r)
1159 opset(AVERIMF, r)
1160 case AVFTCIDB:
1161 opset(AWFTCIDB, r)
1162 case AVLR:
1163 opset(AVUPHB, r)
1164 opset(AVUPHH, r)
1165 opset(AVUPHF, r)
1166 opset(AVUPLHB, r)
1167 opset(AVUPLHH, r)
1168 opset(AVUPLHF, r)
1169 opset(AVUPLB, r)
1170 opset(AVUPLHW, r)
1171 opset(AVUPLF, r)
1172 opset(AVUPLLB, r)
1173 opset(AVUPLLH, r)
1174 opset(AVUPLLF, r)
1175 opset(AVCLZB, r)
1176 opset(AVCLZH, r)
1177 opset(AVCLZF, r)
1178 opset(AVCLZG, r)
1179 opset(AVCTZB, r)
1180 opset(AVCTZH, r)
1181 opset(AVCTZF, r)
1182 opset(AVCTZG, r)
1183 opset(AVLDEB, r)
1184 opset(AWLDEB, r)
1185 opset(AVFLCDB, r)
1186 opset(AWFLCDB, r)
1187 opset(AVFLNDB, r)
1188 opset(AWFLNDB, r)
1189 opset(AVFLPDB, r)
1190 opset(AWFLPDB, r)
1191 opset(AVFSQDB, r)
1192 opset(AWFSQDB, r)
1193 opset(AVISTRB, r)
1194 opset(AVISTRH, r)
1195 opset(AVISTRF, r)
1196 opset(AVISTRBS, r)
1197 opset(AVISTRHS, r)
1198 opset(AVISTRFS, r)
1199 opset(AVLCB, r)
1200 opset(AVLCH, r)
1201 opset(AVLCF, r)
1202 opset(AVLCG, r)
1203 opset(AVLPB, r)
1204 opset(AVLPH, r)
1205 opset(AVLPF, r)
1206 opset(AVLPG, r)
1207 opset(AVPOPCT, r)
1208 opset(AVSEGB, r)
1209 opset(AVSEGH, r)
1210 opset(AVSEGF, r)
1211 case AVECG:
1212 opset(AVECB, r)
1213 opset(AVECH, r)
1214 opset(AVECF, r)
1215 opset(AVECLB, r)
1216 opset(AVECLH, r)
1217 opset(AVECLF, r)
1218 opset(AVECLG, r)
1219 opset(AWFCDB, r)
1220 opset(AWFKDB, r)
1221 case AVCEQG:
1222 opset(AVCEQB, r)
1223 opset(AVCEQH, r)
1224 opset(AVCEQF, r)
1225 opset(AVCEQBS, r)
1226 opset(AVCEQHS, r)
1227 opset(AVCEQFS, r)
1228 opset(AVCEQGS, r)
1229 opset(AVCHB, r)
1230 opset(AVCHH, r)
1231 opset(AVCHF, r)
1232 opset(AVCHG, r)
1233 opset(AVCHBS, r)
1234 opset(AVCHHS, r)
1235 opset(AVCHFS, r)
1236 opset(AVCHGS, r)
1237 opset(AVCHLB, r)
1238 opset(AVCHLH, r)
1239 opset(AVCHLF, r)
1240 opset(AVCHLG, r)
1241 opset(AVCHLBS, r)
1242 opset(AVCHLHS, r)
1243 opset(AVCHLFS, r)
1244 opset(AVCHLGS, r)
1245 case AVFAEF:
1246 opset(AVFAEB, r)
1247 opset(AVFAEH, r)
1248 opset(AVFAEBS, r)
1249 opset(AVFAEHS, r)
1250 opset(AVFAEFS, r)
1251 opset(AVFAEZB, r)
1252 opset(AVFAEZH, r)
1253 opset(AVFAEZF, r)
1254 opset(AVFAEZBS, r)
1255 opset(AVFAEZHS, r)
1256 opset(AVFAEZFS, r)
1257 opset(AVFEEB, r)
1258 opset(AVFEEH, r)
1259 opset(AVFEEF, r)
1260 opset(AVFEEBS, r)
1261 opset(AVFEEHS, r)
1262 opset(AVFEEFS, r)
1263 opset(AVFEEZB, r)
1264 opset(AVFEEZH, r)
1265 opset(AVFEEZF, r)
1266 opset(AVFEEZBS, r)
1267 opset(AVFEEZHS, r)
1268 opset(AVFEEZFS, r)
1269 opset(AVFENEB, r)
1270 opset(AVFENEH, r)
1271 opset(AVFENEF, r)
1272 opset(AVFENEBS, r)
1273 opset(AVFENEHS, r)
1274 opset(AVFENEFS, r)
1275 opset(AVFENEZB, r)
1276 opset(AVFENEZH, r)
1277 opset(AVFENEZF, r)
1278 opset(AVFENEZBS, r)
1279 opset(AVFENEZHS, r)
1280 opset(AVFENEZFS, r)
1281 case AVPKSG:
1282 opset(AVPKSH, r)
1283 opset(AVPKSF, r)
1284 opset(AVPKSHS, r)
1285 opset(AVPKSFS, r)
1286 opset(AVPKSGS, r)
1287 opset(AVPKLSH, r)
1288 opset(AVPKLSF, r)
1289 opset(AVPKLSG, r)
1290 opset(AVPKLSHS, r)
1291 opset(AVPKLSFS, r)
1292 opset(AVPKLSGS, r)
1293 case AVAQ:
1294 opset(AVAB, r)
1295 opset(AVAH, r)
1296 opset(AVAF, r)
1297 opset(AVAG, r)
1298 opset(AVACCB, r)
1299 opset(AVACCH, r)
1300 opset(AVACCF, r)
1301 opset(AVACCG, r)
1302 opset(AVACCQ, r)
1303 opset(AVN, r)
1304 opset(AVNC, r)
1305 opset(AVAVGB, r)
1306 opset(AVAVGH, r)
1307 opset(AVAVGF, r)
1308 opset(AVAVGG, r)
1309 opset(AVAVGLB, r)
1310 opset(AVAVGLH, r)
1311 opset(AVAVGLF, r)
1312 opset(AVAVGLG, r)
1313 opset(AVCKSM, r)
1314 opset(AVX, r)
1315 opset(AVFADB, r)
1316 opset(AWFADB, r)
1317 opset(AVFCEDB, r)
1318 opset(AVFCEDBS, r)
1319 opset(AWFCEDB, r)
1320 opset(AWFCEDBS, r)
1321 opset(AVFCHDB, r)
1322 opset(AVFCHDBS, r)
1323 opset(AWFCHDB, r)
1324 opset(AWFCHDBS, r)
1325 opset(AVFCHEDB, r)
1326 opset(AVFCHEDBS, r)
1327 opset(AWFCHEDB, r)
1328 opset(AWFCHEDBS, r)
1329 opset(AVFMDB, r)
1330 opset(AWFMDB, r)
1331 opset(AVGFMB, r)
1332 opset(AVGFMH, r)
1333 opset(AVGFMF, r)
1334 opset(AVGFMG, r)
1335 opset(AVMXB, r)
1336 opset(AVMXH, r)
1337 opset(AVMXF, r)
1338 opset(AVMXG, r)
1339 opset(AVMXLB, r)
1340 opset(AVMXLH, r)
1341 opset(AVMXLF, r)
1342 opset(AVMXLG, r)
1343 opset(AVMNB, r)
1344 opset(AVMNH, r)
1345 opset(AVMNF, r)
1346 opset(AVMNG, r)
1347 opset(AVMNLB, r)
1348 opset(AVMNLH, r)
1349 opset(AVMNLF, r)
1350 opset(AVMNLG, r)
1351 opset(AVMRHB, r)
1352 opset(AVMRHH, r)
1353 opset(AVMRHF, r)
1354 opset(AVMRHG, r)
1355 opset(AVMRLB, r)
1356 opset(AVMRLH, r)
1357 opset(AVMRLF, r)
1358 opset(AVMRLG, r)
1359 opset(AVMEB, r)
1360 opset(AVMEH, r)
1361 opset(AVMEF, r)
1362 opset(AVMLEB, r)
1363 opset(AVMLEH, r)
1364 opset(AVMLEF, r)
1365 opset(AVMOB, r)
1366 opset(AVMOH, r)
1367 opset(AVMOF, r)
1368 opset(AVMLOB, r)
1369 opset(AVMLOH, r)
1370 opset(AVMLOF, r)
1371 opset(AVMHB, r)
1372 opset(AVMHH, r)
1373 opset(AVMHF, r)
1374 opset(AVMLHB, r)
1375 opset(AVMLHH, r)
1376 opset(AVMLHF, r)
1377 opset(AVMLH, r)
1378 opset(AVMLHW, r)
1379 opset(AVMLF, r)
1380 opset(AVNO, r)
1381 opset(AVO, r)
1382 opset(AVPKH, r)
1383 opset(AVPKF, r)
1384 opset(AVPKG, r)
1385 opset(AVSUMGH, r)
1386 opset(AVSUMGF, r)
1387 opset(AVSUMQF, r)
1388 opset(AVSUMQG, r)
1389 opset(AVSUMB, r)
1390 opset(AVSUMH, r)
1391 case AVERLLVG:
1392 opset(AVERLLVB, r)
1393 opset(AVERLLVH, r)
1394 opset(AVERLLVF, r)
1395 opset(AVESLVB, r)
1396 opset(AVESLVH, r)
1397 opset(AVESLVF, r)
1398 opset(AVESLVG, r)
1399 opset(AVESRAVB, r)
1400 opset(AVESRAVH, r)
1401 opset(AVESRAVF, r)
1402 opset(AVESRAVG, r)
1403 opset(AVESRLVB, r)
1404 opset(AVESRLVH, r)
1405 opset(AVESRLVF, r)
1406 opset(AVESRLVG, r)
1407 opset(AVFDDB, r)
1408 opset(AWFDDB, r)
1409 opset(AVFSDB, r)
1410 opset(AWFSDB, r)
1411 opset(AVSL, r)
1412 opset(AVSLB, r)
1413 opset(AVSRA, r)
1414 opset(AVSRAB, r)
1415 opset(AVSRL, r)
1416 opset(AVSRLB, r)
1417 opset(AVSB, r)
1418 opset(AVSH, r)
1419 opset(AVSF, r)
1420 opset(AVSG, r)
1421 opset(AVSQ, r)
1422 opset(AVSCBIB, r)
1423 opset(AVSCBIH, r)
1424 opset(AVSCBIF, r)
1425 opset(AVSCBIG, r)
1426 opset(AVSCBIQ, r)
1427 case AVACQ:
1428 opset(AVACCCQ, r)
1429 opset(AVGFMAB, r)
1430 opset(AVGFMAH, r)
1431 opset(AVGFMAF, r)
1432 opset(AVGFMAG, r)
1433 opset(AVMALB, r)
1434 opset(AVMALHW, r)
1435 opset(AVMALF, r)
1436 opset(AVMAHB, r)
1437 opset(AVMAHH, r)
1438 opset(AVMAHF, r)
1439 opset(AVMALHB, r)
1440 opset(AVMALHH, r)
1441 opset(AVMALHF, r)
1442 opset(AVMAEB, r)
1443 opset(AVMAEH, r)
1444 opset(AVMAEF, r)
1445 opset(AVMALEB, r)
1446 opset(AVMALEH, r)
1447 opset(AVMALEF, r)
1448 opset(AVMAOB, r)
1449 opset(AVMAOH, r)
1450 opset(AVMAOF, r)
1451 opset(AVMALOB, r)
1452 opset(AVMALOH, r)
1453 opset(AVMALOF, r)
1454 opset(AVSTRC, r)
1455 opset(AVSTRCB, r)
1456 opset(AVSTRCH, r)
1457 opset(AVSTRCF, r)
1458 opset(AVSTRCBS, r)
1459 opset(AVSTRCHS, r)
1460 opset(AVSTRCFS, r)
1461 opset(AVSTRCZB, r)
1462 opset(AVSTRCZH, r)
1463 opset(AVSTRCZF, r)
1464 opset(AVSTRCZBS, r)
1465 opset(AVSTRCZHS, r)
1466 opset(AVSTRCZFS, r)
1467 opset(AVSBCBIQ, r)
1468 opset(AVSBIQ, r)
1469 opset(AVMSLG, r)
1470 opset(AVMSLEG, r)
1471 opset(AVMSLOG, r)
1472 opset(AVMSLEOG, r)
1473 case AVSEL:
1474 opset(AVFMADB, r)
1475 opset(AWFMADB, r)
1476 opset(AVFMSDB, r)
1477 opset(AWFMSDB, r)
1478 opset(AVPERM, r)
1479 case AKM:
1480 opset(AKMC, r)
1481 opset(AKLMD, r)
1482 opset(AKIMD, r)
1483 case AKMA:
1484 opset(AKMCTR, r)
1485 }
1486 }
1487 }
1488
1489 const (
1490 op_A uint32 = 0x5A00
1491 op_AD uint32 = 0x6A00
1492 op_ADB uint32 = 0xED1A
1493 op_ADBR uint32 = 0xB31A
1494 op_ADR uint32 = 0x2A00
1495 op_ADTR uint32 = 0xB3D2
1496 op_ADTRA uint32 = 0xB3D2
1497 op_AE uint32 = 0x7A00
1498 op_AEB uint32 = 0xED0A
1499 op_AEBR uint32 = 0xB30A
1500 op_AER uint32 = 0x3A00
1501 op_AFI uint32 = 0xC209
1502 op_AG uint32 = 0xE308
1503 op_AGF uint32 = 0xE318
1504 op_AGFI uint32 = 0xC208
1505 op_AGFR uint32 = 0xB918
1506 op_AGHI uint32 = 0xA70B
1507 op_AGHIK uint32 = 0xECD9
1508 op_AGR uint32 = 0xB908
1509 op_AGRK uint32 = 0xB9E8
1510 op_AGSI uint32 = 0xEB7A
1511 op_AH uint32 = 0x4A00
1512 op_AHHHR uint32 = 0xB9C8
1513 op_AHHLR uint32 = 0xB9D8
1514 op_AHI uint32 = 0xA70A
1515 op_AHIK uint32 = 0xECD8
1516 op_AHY uint32 = 0xE37A
1517 op_AIH uint32 = 0xCC08
1518 op_AL uint32 = 0x5E00
1519 op_ALC uint32 = 0xE398
1520 op_ALCG uint32 = 0xE388
1521 op_ALCGR uint32 = 0xB988
1522 op_ALCR uint32 = 0xB998
1523 op_ALFI uint32 = 0xC20B
1524 op_ALG uint32 = 0xE30A
1525 op_ALGF uint32 = 0xE31A
1526 op_ALGFI uint32 = 0xC20A
1527 op_ALGFR uint32 = 0xB91A
1528 op_ALGHSIK uint32 = 0xECDB
1529 op_ALGR uint32 = 0xB90A
1530 op_ALGRK uint32 = 0xB9EA
1531 op_ALGSI uint32 = 0xEB7E
1532 op_ALHHHR uint32 = 0xB9CA
1533 op_ALHHLR uint32 = 0xB9DA
1534 op_ALHSIK uint32 = 0xECDA
1535 op_ALR uint32 = 0x1E00
1536 op_ALRK uint32 = 0xB9FA
1537 op_ALSI uint32 = 0xEB6E
1538 op_ALSIH uint32 = 0xCC0A
1539 op_ALSIHN uint32 = 0xCC0B
1540 op_ALY uint32 = 0xE35E
1541 op_AP uint32 = 0xFA00
1542 op_AR uint32 = 0x1A00
1543 op_ARK uint32 = 0xB9F8
1544 op_ASI uint32 = 0xEB6A
1545 op_AU uint32 = 0x7E00
1546 op_AUR uint32 = 0x3E00
1547 op_AW uint32 = 0x6E00
1548 op_AWR uint32 = 0x2E00
1549 op_AXBR uint32 = 0xB34A
1550 op_AXR uint32 = 0x3600
1551 op_AXTR uint32 = 0xB3DA
1552 op_AXTRA uint32 = 0xB3DA
1553 op_AY uint32 = 0xE35A
1554 op_BAKR uint32 = 0xB240
1555 op_BAL uint32 = 0x4500
1556 op_BALR uint32 = 0x0500
1557 op_BAS uint32 = 0x4D00
1558 op_BASR uint32 = 0x0D00
1559 op_BASSM uint32 = 0x0C00
1560 op_BC uint32 = 0x4700
1561 op_BCR uint32 = 0x0700
1562 op_BCT uint32 = 0x4600
1563 op_BCTG uint32 = 0xE346
1564 op_BCTGR uint32 = 0xB946
1565 op_BCTR uint32 = 0x0600
1566 op_BPP uint32 = 0xC700
1567 op_BPRP uint32 = 0xC500
1568 op_BRAS uint32 = 0xA705
1569 op_BRASL uint32 = 0xC005
1570 op_BRC uint32 = 0xA704
1571 op_BRCL uint32 = 0xC004
1572 op_BRCT uint32 = 0xA706
1573 op_BRCTG uint32 = 0xA707
1574 op_BRCTH uint32 = 0xCC06
1575 op_BRXH uint32 = 0x8400
1576 op_BRXHG uint32 = 0xEC44
1577 op_BRXLE uint32 = 0x8500
1578 op_BRXLG uint32 = 0xEC45
1579 op_BSA uint32 = 0xB25A
1580 op_BSG uint32 = 0xB258
1581 op_BSM uint32 = 0x0B00
1582 op_BXH uint32 = 0x8600
1583 op_BXHG uint32 = 0xEB44
1584 op_BXLE uint32 = 0x8700
1585 op_BXLEG uint32 = 0xEB45
1586 op_C uint32 = 0x5900
1587 op_CD uint32 = 0x6900
1588 op_CDB uint32 = 0xED19
1589 op_CDBR uint32 = 0xB319
1590 op_CDFBR uint32 = 0xB395
1591 op_CDFBRA uint32 = 0xB395
1592 op_CDFR uint32 = 0xB3B5
1593 op_CDFTR uint32 = 0xB951
1594 op_CDGBR uint32 = 0xB3A5
1595 op_CDGBRA uint32 = 0xB3A5
1596 op_CDGR uint32 = 0xB3C5
1597 op_CDGTR uint32 = 0xB3F1
1598 op_CDGTRA uint32 = 0xB3F1
1599 op_CDLFBR uint32 = 0xB391
1600 op_CDLFTR uint32 = 0xB953
1601 op_CDLGBR uint32 = 0xB3A1
1602 op_CDLGTR uint32 = 0xB952
1603 op_CDR uint32 = 0x2900
1604 op_CDS uint32 = 0xBB00
1605 op_CDSG uint32 = 0xEB3E
1606 op_CDSTR uint32 = 0xB3F3
1607 op_CDSY uint32 = 0xEB31
1608 op_CDTR uint32 = 0xB3E4
1609 op_CDUTR uint32 = 0xB3F2
1610 op_CDZT uint32 = 0xEDAA
1611 op_CE uint32 = 0x7900
1612 op_CEB uint32 = 0xED09
1613 op_CEBR uint32 = 0xB309
1614 op_CEDTR uint32 = 0xB3F4
1615 op_CEFBR uint32 = 0xB394
1616 op_CEFBRA uint32 = 0xB394
1617 op_CEFR uint32 = 0xB3B4
1618 op_CEGBR uint32 = 0xB3A4
1619 op_CEGBRA uint32 = 0xB3A4
1620 op_CEGR uint32 = 0xB3C4
1621 op_CELFBR uint32 = 0xB390
1622 op_CELGBR uint32 = 0xB3A0
1623 op_CER uint32 = 0x3900
1624 op_CEXTR uint32 = 0xB3FC
1625 op_CFC uint32 = 0xB21A
1626 op_CFDBR uint32 = 0xB399
1627 op_CFDBRA uint32 = 0xB399
1628 op_CFDR uint32 = 0xB3B9
1629 op_CFDTR uint32 = 0xB941
1630 op_CFEBR uint32 = 0xB398
1631 op_CFEBRA uint32 = 0xB398
1632 op_CFER uint32 = 0xB3B8
1633 op_CFI uint32 = 0xC20D
1634 op_CFXBR uint32 = 0xB39A
1635 op_CFXBRA uint32 = 0xB39A
1636 op_CFXR uint32 = 0xB3BA
1637 op_CFXTR uint32 = 0xB949
1638 op_CG uint32 = 0xE320
1639 op_CGDBR uint32 = 0xB3A9
1640 op_CGDBRA uint32 = 0xB3A9
1641 op_CGDR uint32 = 0xB3C9
1642 op_CGDTR uint32 = 0xB3E1
1643 op_CGDTRA uint32 = 0xB3E1
1644 op_CGEBR uint32 = 0xB3A8
1645 op_CGEBRA uint32 = 0xB3A8
1646 op_CGER uint32 = 0xB3C8
1647 op_CGF uint32 = 0xE330
1648 op_CGFI uint32 = 0xC20C
1649 op_CGFR uint32 = 0xB930
1650 op_CGFRL uint32 = 0xC60C
1651 op_CGH uint32 = 0xE334
1652 op_CGHI uint32 = 0xA70F
1653 op_CGHRL uint32 = 0xC604
1654 op_CGHSI uint32 = 0xE558
1655 op_CGIB uint32 = 0xECFC
1656 op_CGIJ uint32 = 0xEC7C
1657 op_CGIT uint32 = 0xEC70
1658 op_CGR uint32 = 0xB920
1659 op_CGRB uint32 = 0xECE4
1660 op_CGRJ uint32 = 0xEC64
1661 op_CGRL uint32 = 0xC608
1662 op_CGRT uint32 = 0xB960
1663 op_CGXBR uint32 = 0xB3AA
1664 op_CGXBRA uint32 = 0xB3AA
1665 op_CGXR uint32 = 0xB3CA
1666 op_CGXTR uint32 = 0xB3E9
1667 op_CGXTRA uint32 = 0xB3E9
1668 op_CH uint32 = 0x4900
1669 op_CHF uint32 = 0xE3CD
1670 op_CHHR uint32 = 0xB9CD
1671 op_CHHSI uint32 = 0xE554
1672 op_CHI uint32 = 0xA70E
1673 op_CHLR uint32 = 0xB9DD
1674 op_CHRL uint32 = 0xC605
1675 op_CHSI uint32 = 0xE55C
1676 op_CHY uint32 = 0xE379
1677 op_CIB uint32 = 0xECFE
1678 op_CIH uint32 = 0xCC0D
1679 op_CIJ uint32 = 0xEC7E
1680 op_CIT uint32 = 0xEC72
1681 op_CKSM uint32 = 0xB241
1682 op_CL uint32 = 0x5500
1683 op_CLC uint32 = 0xD500
1684 op_CLCL uint32 = 0x0F00
1685 op_CLCLE uint32 = 0xA900
1686 op_CLCLU uint32 = 0xEB8F
1687 op_CLFDBR uint32 = 0xB39D
1688 op_CLFDTR uint32 = 0xB943
1689 op_CLFEBR uint32 = 0xB39C
1690 op_CLFHSI uint32 = 0xE55D
1691 op_CLFI uint32 = 0xC20F
1692 op_CLFIT uint32 = 0xEC73
1693 op_CLFXBR uint32 = 0xB39E
1694 op_CLFXTR uint32 = 0xB94B
1695 op_CLG uint32 = 0xE321
1696 op_CLGDBR uint32 = 0xB3AD
1697 op_CLGDTR uint32 = 0xB942
1698 op_CLGEBR uint32 = 0xB3AC
1699 op_CLGF uint32 = 0xE331
1700 op_CLGFI uint32 = 0xC20E
1701 op_CLGFR uint32 = 0xB931
1702 op_CLGFRL uint32 = 0xC60E
1703 op_CLGHRL uint32 = 0xC606
1704 op_CLGHSI uint32 = 0xE559
1705 op_CLGIB uint32 = 0xECFD
1706 op_CLGIJ uint32 = 0xEC7D
1707 op_CLGIT uint32 = 0xEC71
1708 op_CLGR uint32 = 0xB921
1709 op_CLGRB uint32 = 0xECE5
1710 op_CLGRJ uint32 = 0xEC65
1711 op_CLGRL uint32 = 0xC60A
1712 op_CLGRT uint32 = 0xB961
1713 op_CLGT uint32 = 0xEB2B
1714 op_CLGXBR uint32 = 0xB3AE
1715 op_CLGXTR uint32 = 0xB94A
1716 op_CLHF uint32 = 0xE3CF
1717 op_CLHHR uint32 = 0xB9CF
1718 op_CLHHSI uint32 = 0xE555
1719 op_CLHLR uint32 = 0xB9DF
1720 op_CLHRL uint32 = 0xC607
1721 op_CLI uint32 = 0x9500
1722 op_CLIB uint32 = 0xECFF
1723 op_CLIH uint32 = 0xCC0F
1724 op_CLIJ uint32 = 0xEC7F
1725 op_CLIY uint32 = 0xEB55
1726 op_CLM uint32 = 0xBD00
1727 op_CLMH uint32 = 0xEB20
1728 op_CLMY uint32 = 0xEB21
1729 op_CLR uint32 = 0x1500
1730 op_CLRB uint32 = 0xECF7
1731 op_CLRJ uint32 = 0xEC77
1732 op_CLRL uint32 = 0xC60F
1733 op_CLRT uint32 = 0xB973
1734 op_CLST uint32 = 0xB25D
1735 op_CLT uint32 = 0xEB23
1736 op_CLY uint32 = 0xE355
1737 op_CMPSC uint32 = 0xB263
1738 op_CP uint32 = 0xF900
1739 op_CPSDR uint32 = 0xB372
1740 op_CPYA uint32 = 0xB24D
1741 op_CR uint32 = 0x1900
1742 op_CRB uint32 = 0xECF6
1743 op_CRDTE uint32 = 0xB98F
1744 op_CRJ uint32 = 0xEC76
1745 op_CRL uint32 = 0xC60D
1746 op_CRT uint32 = 0xB972
1747 op_CS uint32 = 0xBA00
1748 op_CSCH uint32 = 0xB230
1749 op_CSDTR uint32 = 0xB3E3
1750 op_CSG uint32 = 0xEB30
1751 op_CSP uint32 = 0xB250
1752 op_CSPG uint32 = 0xB98A
1753 op_CSST uint32 = 0xC802
1754 op_CSXTR uint32 = 0xB3EB
1755 op_CSY uint32 = 0xEB14
1756 op_CU12 uint32 = 0xB2A7
1757 op_CU14 uint32 = 0xB9B0
1758 op_CU21 uint32 = 0xB2A6
1759 op_CU24 uint32 = 0xB9B1
1760 op_CU41 uint32 = 0xB9B2
1761 op_CU42 uint32 = 0xB9B3
1762 op_CUDTR uint32 = 0xB3E2
1763 op_CUSE uint32 = 0xB257
1764 op_CUTFU uint32 = 0xB2A7
1765 op_CUUTF uint32 = 0xB2A6
1766 op_CUXTR uint32 = 0xB3EA
1767 op_CVB uint32 = 0x4F00
1768 op_CVBG uint32 = 0xE30E
1769 op_CVBY uint32 = 0xE306
1770 op_CVD uint32 = 0x4E00
1771 op_CVDG uint32 = 0xE32E
1772 op_CVDY uint32 = 0xE326
1773 op_CXBR uint32 = 0xB349
1774 op_CXFBR uint32 = 0xB396
1775 op_CXFBRA uint32 = 0xB396
1776 op_CXFR uint32 = 0xB3B6
1777 op_CXFTR uint32 = 0xB959
1778 op_CXGBR uint32 = 0xB3A6
1779 op_CXGBRA uint32 = 0xB3A6
1780 op_CXGR uint32 = 0xB3C6
1781 op_CXGTR uint32 = 0xB3F9
1782 op_CXGTRA uint32 = 0xB3F9
1783 op_CXLFBR uint32 = 0xB392
1784 op_CXLFTR uint32 = 0xB95B
1785 op_CXLGBR uint32 = 0xB3A2
1786 op_CXLGTR uint32 = 0xB95A
1787 op_CXR uint32 = 0xB369
1788 op_CXSTR uint32 = 0xB3FB
1789 op_CXTR uint32 = 0xB3EC
1790 op_CXUTR uint32 = 0xB3FA
1791 op_CXZT uint32 = 0xEDAB
1792 op_CY uint32 = 0xE359
1793 op_CZDT uint32 = 0xEDA8
1794 op_CZXT uint32 = 0xEDA9
1795 op_D uint32 = 0x5D00
1796 op_DD uint32 = 0x6D00
1797 op_DDB uint32 = 0xED1D
1798 op_DDBR uint32 = 0xB31D
1799 op_DDR uint32 = 0x2D00
1800 op_DDTR uint32 = 0xB3D1
1801 op_DDTRA uint32 = 0xB3D1
1802 op_DE uint32 = 0x7D00
1803 op_DEB uint32 = 0xED0D
1804 op_DEBR uint32 = 0xB30D
1805 op_DER uint32 = 0x3D00
1806 op_DIDBR uint32 = 0xB35B
1807 op_DIEBR uint32 = 0xB353
1808 op_DL uint32 = 0xE397
1809 op_DLG uint32 = 0xE387
1810 op_DLGR uint32 = 0xB987
1811 op_DLR uint32 = 0xB997
1812 op_DP uint32 = 0xFD00
1813 op_DR uint32 = 0x1D00
1814 op_DSG uint32 = 0xE30D
1815 op_DSGF uint32 = 0xE31D
1816 op_DSGFR uint32 = 0xB91D
1817 op_DSGR uint32 = 0xB90D
1818 op_DXBR uint32 = 0xB34D
1819 op_DXR uint32 = 0xB22D
1820 op_DXTR uint32 = 0xB3D9
1821 op_DXTRA uint32 = 0xB3D9
1822 op_EAR uint32 = 0xB24F
1823 op_ECAG uint32 = 0xEB4C
1824 op_ECTG uint32 = 0xC801
1825 op_ED uint32 = 0xDE00
1826 op_EDMK uint32 = 0xDF00
1827 op_EEDTR uint32 = 0xB3E5
1828 op_EEXTR uint32 = 0xB3ED
1829 op_EFPC uint32 = 0xB38C
1830 op_EPAIR uint32 = 0xB99A
1831 op_EPAR uint32 = 0xB226
1832 op_EPSW uint32 = 0xB98D
1833 op_EREG uint32 = 0xB249
1834 op_EREGG uint32 = 0xB90E
1835 op_ESAIR uint32 = 0xB99B
1836 op_ESAR uint32 = 0xB227
1837 op_ESDTR uint32 = 0xB3E7
1838 op_ESEA uint32 = 0xB99D
1839 op_ESTA uint32 = 0xB24A
1840 op_ESXTR uint32 = 0xB3EF
1841 op_ETND uint32 = 0xB2EC
1842 op_EX uint32 = 0x4400
1843 op_EXRL uint32 = 0xC600
1844 op_FIDBR uint32 = 0xB35F
1845 op_FIDBRA uint32 = 0xB35F
1846 op_FIDR uint32 = 0xB37F
1847 op_FIDTR uint32 = 0xB3D7
1848 op_FIEBR uint32 = 0xB357
1849 op_FIEBRA uint32 = 0xB357
1850 op_FIER uint32 = 0xB377
1851 op_FIXBR uint32 = 0xB347
1852 op_FIXBRA uint32 = 0xB347
1853 op_FIXR uint32 = 0xB367
1854 op_FIXTR uint32 = 0xB3DF
1855 op_FLOGR uint32 = 0xB983
1856 op_HDR uint32 = 0x2400
1857 op_HER uint32 = 0x3400
1858 op_HSCH uint32 = 0xB231
1859 op_IAC uint32 = 0xB224
1860 op_IC uint32 = 0x4300
1861 op_ICM uint32 = 0xBF00
1862 op_ICMH uint32 = 0xEB80
1863 op_ICMY uint32 = 0xEB81
1864 op_ICY uint32 = 0xE373
1865 op_IDTE uint32 = 0xB98E
1866 op_IEDTR uint32 = 0xB3F6
1867 op_IEXTR uint32 = 0xB3FE
1868 op_IIHF uint32 = 0xC008
1869 op_IIHH uint32 = 0xA500
1870 op_IIHL uint32 = 0xA501
1871 op_IILF uint32 = 0xC009
1872 op_IILH uint32 = 0xA502
1873 op_IILL uint32 = 0xA503
1874 op_IPK uint32 = 0xB20B
1875 op_IPM uint32 = 0xB222
1876 op_IPTE uint32 = 0xB221
1877 op_ISKE uint32 = 0xB229
1878 op_IVSK uint32 = 0xB223
1879 op_KDB uint32 = 0xED18
1880 op_KDBR uint32 = 0xB318
1881 op_KDTR uint32 = 0xB3E0
1882 op_KEB uint32 = 0xED08
1883 op_KEBR uint32 = 0xB308
1884 op_KIMD uint32 = 0xB93E
1885 op_KLMD uint32 = 0xB93F
1886 op_KM uint32 = 0xB92E
1887 op_KMAC uint32 = 0xB91E
1888 op_KMC uint32 = 0xB92F
1889 op_KMA uint32 = 0xB929
1890 op_KMCTR uint32 = 0xB92D
1891 op_KMF uint32 = 0xB92A
1892 op_KMO uint32 = 0xB92B
1893 op_KXBR uint32 = 0xB348
1894 op_KXTR uint32 = 0xB3E8
1895 op_L uint32 = 0x5800
1896 op_LA uint32 = 0x4100
1897 op_LAA uint32 = 0xEBF8
1898 op_LAAG uint32 = 0xEBE8
1899 op_LAAL uint32 = 0xEBFA
1900 op_LAALG uint32 = 0xEBEA
1901 op_LAE uint32 = 0x5100
1902 op_LAEY uint32 = 0xE375
1903 op_LAM uint32 = 0x9A00
1904 op_LAMY uint32 = 0xEB9A
1905 op_LAN uint32 = 0xEBF4
1906 op_LANG uint32 = 0xEBE4
1907 op_LAO uint32 = 0xEBF6
1908 op_LAOG uint32 = 0xEBE6
1909 op_LARL uint32 = 0xC000
1910 op_LASP uint32 = 0xE500
1911 op_LAT uint32 = 0xE39F
1912 op_LAX uint32 = 0xEBF7
1913 op_LAXG uint32 = 0xEBE7
1914 op_LAY uint32 = 0xE371
1915 op_LB uint32 = 0xE376
1916 op_LBH uint32 = 0xE3C0
1917 op_LBR uint32 = 0xB926
1918 op_LCDBR uint32 = 0xB313
1919 op_LCDFR uint32 = 0xB373
1920 op_LCDR uint32 = 0x2300
1921 op_LCEBR uint32 = 0xB303
1922 op_LCER uint32 = 0x3300
1923 op_LCGFR uint32 = 0xB913
1924 op_LCGR uint32 = 0xB903
1925 op_LCR uint32 = 0x1300
1926 op_LCTL uint32 = 0xB700
1927 op_LCTLG uint32 = 0xEB2F
1928 op_LCXBR uint32 = 0xB343
1929 op_LCXR uint32 = 0xB363
1930 op_LD uint32 = 0x6800
1931 op_LDE uint32 = 0xED24
1932 op_LDEB uint32 = 0xED04
1933 op_LDEBR uint32 = 0xB304
1934 op_LDER uint32 = 0xB324
1935 op_LDETR uint32 = 0xB3D4
1936 op_LDGR uint32 = 0xB3C1
1937 op_LDR uint32 = 0x2800
1938 op_LDXBR uint32 = 0xB345
1939 op_LDXBRA uint32 = 0xB345
1940 op_LDXR uint32 = 0x2500
1941 op_LDXTR uint32 = 0xB3DD
1942 op_LDY uint32 = 0xED65
1943 op_LE uint32 = 0x7800
1944 op_LEDBR uint32 = 0xB344
1945 op_LEDBRA uint32 = 0xB344
1946 op_LEDR uint32 = 0x3500
1947 op_LEDTR uint32 = 0xB3D5
1948 op_LER uint32 = 0x3800
1949 op_LEXBR uint32 = 0xB346
1950 op_LEXBRA uint32 = 0xB346
1951 op_LEXR uint32 = 0xB366
1952 op_LEY uint32 = 0xED64
1953 op_LFAS uint32 = 0xB2BD
1954 op_LFH uint32 = 0xE3CA
1955 op_LFHAT uint32 = 0xE3C8
1956 op_LFPC uint32 = 0xB29D
1957 op_LG uint32 = 0xE304
1958 op_LGAT uint32 = 0xE385
1959 op_LGB uint32 = 0xE377
1960 op_LGBR uint32 = 0xB906
1961 op_LGDR uint32 = 0xB3CD
1962 op_LGF uint32 = 0xE314
1963 op_LGFI uint32 = 0xC001
1964 op_LGFR uint32 = 0xB914
1965 op_LGFRL uint32 = 0xC40C
1966 op_LGH uint32 = 0xE315
1967 op_LGHI uint32 = 0xA709
1968 op_LGHR uint32 = 0xB907
1969 op_LGHRL uint32 = 0xC404
1970 op_LGR uint32 = 0xB904
1971 op_LGRL uint32 = 0xC408
1972 op_LH uint32 = 0x4800
1973 op_LHH uint32 = 0xE3C4
1974 op_LHI uint32 = 0xA708
1975 op_LHR uint32 = 0xB927
1976 op_LHRL uint32 = 0xC405
1977 op_LHY uint32 = 0xE378
1978 op_LLC uint32 = 0xE394
1979 op_LLCH uint32 = 0xE3C2
1980 op_LLCR uint32 = 0xB994
1981 op_LLGC uint32 = 0xE390
1982 op_LLGCR uint32 = 0xB984
1983 op_LLGF uint32 = 0xE316
1984 op_LLGFAT uint32 = 0xE39D
1985 op_LLGFR uint32 = 0xB916
1986 op_LLGFRL uint32 = 0xC40E
1987 op_LLGH uint32 = 0xE391
1988 op_LLGHR uint32 = 0xB985
1989 op_LLGHRL uint32 = 0xC406
1990 op_LLGT uint32 = 0xE317
1991 op_LLGTAT uint32 = 0xE39C
1992 op_LLGTR uint32 = 0xB917
1993 op_LLH uint32 = 0xE395
1994 op_LLHH uint32 = 0xE3C6
1995 op_LLHR uint32 = 0xB995
1996 op_LLHRL uint32 = 0xC402
1997 op_LLIHF uint32 = 0xC00E
1998 op_LLIHH uint32 = 0xA50C
1999 op_LLIHL uint32 = 0xA50D
2000 op_LLILF uint32 = 0xC00F
2001 op_LLILH uint32 = 0xA50E
2002 op_LLILL uint32 = 0xA50F
2003 op_LM uint32 = 0x9800
2004 op_LMD uint32 = 0xEF00
2005 op_LMG uint32 = 0xEB04
2006 op_LMH uint32 = 0xEB96
2007 op_LMY uint32 = 0xEB98
2008 op_LNDBR uint32 = 0xB311
2009 op_LNDFR uint32 = 0xB371
2010 op_LNDR uint32 = 0x2100
2011 op_LNEBR uint32 = 0xB301
2012 op_LNER uint32 = 0x3100
2013 op_LNGFR uint32 = 0xB911
2014 op_LNGR uint32 = 0xB901
2015 op_LNR uint32 = 0x1100
2016 op_LNXBR uint32 = 0xB341
2017 op_LNXR uint32 = 0xB361
2018 op_LOC uint32 = 0xEBF2
2019 op_LOCG uint32 = 0xEBE2
2020 op_LOCGR uint32 = 0xB9E2
2021 op_LOCR uint32 = 0xB9F2
2022 op_LPD uint32 = 0xC804
2023 op_LPDBR uint32 = 0xB310
2024 op_LPDFR uint32 = 0xB370
2025 op_LPDG uint32 = 0xC805
2026 op_LPDR uint32 = 0x2000
2027 op_LPEBR uint32 = 0xB300
2028 op_LPER uint32 = 0x3000
2029 op_LPGFR uint32 = 0xB910
2030 op_LPGR uint32 = 0xB900
2031 op_LPQ uint32 = 0xE38F
2032 op_LPR uint32 = 0x1000
2033 op_LPSW uint32 = 0x8200
2034 op_LPSWE uint32 = 0xB2B2
2035 op_LPTEA uint32 = 0xB9AA
2036 op_LPXBR uint32 = 0xB340
2037 op_LPXR uint32 = 0xB360
2038 op_LR uint32 = 0x1800
2039 op_LRA uint32 = 0xB100
2040 op_LRAG uint32 = 0xE303
2041 op_LRAY uint32 = 0xE313
2042 op_LRDR uint32 = 0x2500
2043 op_LRER uint32 = 0x3500
2044 op_LRL uint32 = 0xC40D
2045 op_LRV uint32 = 0xE31E
2046 op_LRVG uint32 = 0xE30F
2047 op_LRVGR uint32 = 0xB90F
2048 op_LRVH uint32 = 0xE31F
2049 op_LRVR uint32 = 0xB91F
2050 op_LT uint32 = 0xE312
2051 op_LTDBR uint32 = 0xB312
2052 op_LTDR uint32 = 0x2200
2053 op_LTDTR uint32 = 0xB3D6
2054 op_LTEBR uint32 = 0xB302
2055 op_LTER uint32 = 0x3200
2056 op_LTG uint32 = 0xE302
2057 op_LTGF uint32 = 0xE332
2058 op_LTGFR uint32 = 0xB912
2059 op_LTGR uint32 = 0xB902
2060 op_LTR uint32 = 0x1200
2061 op_LTXBR uint32 = 0xB342
2062 op_LTXR uint32 = 0xB362
2063 op_LTXTR uint32 = 0xB3DE
2064 op_LURA uint32 = 0xB24B
2065 op_LURAG uint32 = 0xB905
2066 op_LXD uint32 = 0xED25
2067 op_LXDB uint32 = 0xED05
2068 op_LXDBR uint32 = 0xB305
2069 op_LXDR uint32 = 0xB325
2070 op_LXDTR uint32 = 0xB3DC
2071 op_LXE uint32 = 0xED26
2072 op_LXEB uint32 = 0xED06
2073 op_LXEBR uint32 = 0xB306
2074 op_LXER uint32 = 0xB326
2075 op_LXR uint32 = 0xB365
2076 op_LY uint32 = 0xE358
2077 op_LZDR uint32 = 0xB375
2078 op_LZER uint32 = 0xB374
2079 op_LZXR uint32 = 0xB376
2080 op_M uint32 = 0x5C00
2081 op_MAD uint32 = 0xED3E
2082 op_MADB uint32 = 0xED1E
2083 op_MADBR uint32 = 0xB31E
2084 op_MADR uint32 = 0xB33E
2085 op_MAE uint32 = 0xED2E
2086 op_MAEB uint32 = 0xED0E
2087 op_MAEBR uint32 = 0xB30E
2088 op_MAER uint32 = 0xB32E
2089 op_MAY uint32 = 0xED3A
2090 op_MAYH uint32 = 0xED3C
2091 op_MAYHR uint32 = 0xB33C
2092 op_MAYL uint32 = 0xED38
2093 op_MAYLR uint32 = 0xB338
2094 op_MAYR uint32 = 0xB33A
2095 op_MC uint32 = 0xAF00
2096 op_MD uint32 = 0x6C00
2097 op_MDB uint32 = 0xED1C
2098 op_MDBR uint32 = 0xB31C
2099 op_MDE uint32 = 0x7C00
2100 op_MDEB uint32 = 0xED0C
2101 op_MDEBR uint32 = 0xB30C
2102 op_MDER uint32 = 0x3C00
2103 op_MDR uint32 = 0x2C00
2104 op_MDTR uint32 = 0xB3D0
2105 op_MDTRA uint32 = 0xB3D0
2106 op_ME uint32 = 0x7C00
2107 op_MEE uint32 = 0xED37
2108 op_MEEB uint32 = 0xED17
2109 op_MEEBR uint32 = 0xB317
2110 op_MEER uint32 = 0xB337
2111 op_MER uint32 = 0x3C00
2112 op_MFY uint32 = 0xE35C
2113 op_MGHI uint32 = 0xA70D
2114 op_MH uint32 = 0x4C00
2115 op_MHI uint32 = 0xA70C
2116 op_MHY uint32 = 0xE37C
2117 op_ML uint32 = 0xE396
2118 op_MLG uint32 = 0xE386
2119 op_MLGR uint32 = 0xB986
2120 op_MLR uint32 = 0xB996
2121 op_MP uint32 = 0xFC00
2122 op_MR uint32 = 0x1C00
2123 op_MS uint32 = 0x7100
2124 op_MSCH uint32 = 0xB232
2125 op_MSD uint32 = 0xED3F
2126 op_MSDB uint32 = 0xED1F
2127 op_MSDBR uint32 = 0xB31F
2128 op_MSDR uint32 = 0xB33F
2129 op_MSE uint32 = 0xED2F
2130 op_MSEB uint32 = 0xED0F
2131 op_MSEBR uint32 = 0xB30F
2132 op_MSER uint32 = 0xB32F
2133 op_MSFI uint32 = 0xC201
2134 op_MSG uint32 = 0xE30C
2135 op_MSGF uint32 = 0xE31C
2136 op_MSGFI uint32 = 0xC200
2137 op_MSGFR uint32 = 0xB91C
2138 op_MSGR uint32 = 0xB90C
2139 op_MSR uint32 = 0xB252
2140 op_MSTA uint32 = 0xB247
2141 op_MSY uint32 = 0xE351
2142 op_MVC uint32 = 0xD200
2143 op_MVCDK uint32 = 0xE50F
2144 op_MVCIN uint32 = 0xE800
2145 op_MVCK uint32 = 0xD900
2146 op_MVCL uint32 = 0x0E00
2147 op_MVCLE uint32 = 0xA800
2148 op_MVCLU uint32 = 0xEB8E
2149 op_MVCOS uint32 = 0xC800
2150 op_MVCP uint32 = 0xDA00
2151 op_MVCS uint32 = 0xDB00
2152 op_MVCSK uint32 = 0xE50E
2153 op_MVGHI uint32 = 0xE548
2154 op_MVHHI uint32 = 0xE544
2155 op_MVHI uint32 = 0xE54C
2156 op_MVI uint32 = 0x9200
2157 op_MVIY uint32 = 0xEB52
2158 op_MVN uint32 = 0xD100
2159 op_MVO uint32 = 0xF100
2160 op_MVPG uint32 = 0xB254
2161 op_MVST uint32 = 0xB255
2162 op_MVZ uint32 = 0xD300
2163 op_MXBR uint32 = 0xB34C
2164 op_MXD uint32 = 0x6700
2165 op_MXDB uint32 = 0xED07
2166 op_MXDBR uint32 = 0xB307
2167 op_MXDR uint32 = 0x2700
2168 op_MXR uint32 = 0x2600
2169 op_MXTR uint32 = 0xB3D8
2170 op_MXTRA uint32 = 0xB3D8
2171 op_MY uint32 = 0xED3B
2172 op_MYH uint32 = 0xED3D
2173 op_MYHR uint32 = 0xB33D
2174 op_MYL uint32 = 0xED39
2175 op_MYLR uint32 = 0xB339
2176 op_MYR uint32 = 0xB33B
2177 op_N uint32 = 0x5400
2178 op_NC uint32 = 0xD400
2179 op_NG uint32 = 0xE380
2180 op_NGR uint32 = 0xB980
2181 op_NGRK uint32 = 0xB9E4
2182 op_NI uint32 = 0x9400
2183 op_NIAI uint32 = 0xB2FA
2184 op_NIHF uint32 = 0xC00A
2185 op_NIHH uint32 = 0xA504
2186 op_NIHL uint32 = 0xA505
2187 op_NILF uint32 = 0xC00B
2188 op_NILH uint32 = 0xA506
2189 op_NILL uint32 = 0xA507
2190 op_NIY uint32 = 0xEB54
2191 op_NR uint32 = 0x1400
2192 op_NRK uint32 = 0xB9F4
2193 op_NTSTG uint32 = 0xE325
2194 op_NY uint32 = 0xE354
2195 op_O uint32 = 0x5600
2196 op_OC uint32 = 0xD600
2197 op_OG uint32 = 0xE381
2198 op_OGR uint32 = 0xB981
2199 op_OGRK uint32 = 0xB9E6
2200 op_OI uint32 = 0x9600
2201 op_OIHF uint32 = 0xC00C
2202 op_OIHH uint32 = 0xA508
2203 op_OIHL uint32 = 0xA509
2204 op_OILF uint32 = 0xC00D
2205 op_OILH uint32 = 0xA50A
2206 op_OILL uint32 = 0xA50B
2207 op_OIY uint32 = 0xEB56
2208 op_OR uint32 = 0x1600
2209 op_ORK uint32 = 0xB9F6
2210 op_OY uint32 = 0xE356
2211 op_PACK uint32 = 0xF200
2212 op_PALB uint32 = 0xB248
2213 op_PC uint32 = 0xB218
2214 op_PCC uint32 = 0xB92C
2215 op_PCKMO uint32 = 0xB928
2216 op_PFD uint32 = 0xE336
2217 op_PFDRL uint32 = 0xC602
2218 op_PFMF uint32 = 0xB9AF
2219 op_PFPO uint32 = 0x010A
2220 op_PGIN uint32 = 0xB22E
2221 op_PGOUT uint32 = 0xB22F
2222 op_PKA uint32 = 0xE900
2223 op_PKU uint32 = 0xE100
2224 op_PLO uint32 = 0xEE00
2225 op_POPCNT uint32 = 0xB9E1
2226 op_PPA uint32 = 0xB2E8
2227 op_PR uint32 = 0x0101
2228 op_PT uint32 = 0xB228
2229 op_PTF uint32 = 0xB9A2
2230 op_PTFF uint32 = 0x0104
2231 op_PTI uint32 = 0xB99E
2232 op_PTLB uint32 = 0xB20D
2233 op_QADTR uint32 = 0xB3F5
2234 op_QAXTR uint32 = 0xB3FD
2235 op_RCHP uint32 = 0xB23B
2236 op_RISBG uint32 = 0xEC55
2237 op_RISBGN uint32 = 0xEC59
2238 op_RISBHG uint32 = 0xEC5D
2239 op_RISBLG uint32 = 0xEC51
2240 op_RLL uint32 = 0xEB1D
2241 op_RLLG uint32 = 0xEB1C
2242 op_RNSBG uint32 = 0xEC54
2243 op_ROSBG uint32 = 0xEC56
2244 op_RP uint32 = 0xB277
2245 op_RRBE uint32 = 0xB22A
2246 op_RRBM uint32 = 0xB9AE
2247 op_RRDTR uint32 = 0xB3F7
2248 op_RRXTR uint32 = 0xB3FF
2249 op_RSCH uint32 = 0xB238
2250 op_RXSBG uint32 = 0xEC57
2251 op_S uint32 = 0x5B00
2252 op_SAC uint32 = 0xB219
2253 op_SACF uint32 = 0xB279
2254 op_SAL uint32 = 0xB237
2255 op_SAM24 uint32 = 0x010C
2256 op_SAM31 uint32 = 0x010D
2257 op_SAM64 uint32 = 0x010E
2258 op_SAR uint32 = 0xB24E
2259 op_SCHM uint32 = 0xB23C
2260 op_SCK uint32 = 0xB204
2261 op_SCKC uint32 = 0xB206
2262 op_SCKPF uint32 = 0x0107
2263 op_SD uint32 = 0x6B00
2264 op_SDB uint32 = 0xED1B
2265 op_SDBR uint32 = 0xB31B
2266 op_SDR uint32 = 0x2B00
2267 op_SDTR uint32 = 0xB3D3
2268 op_SDTRA uint32 = 0xB3D3
2269 op_SE uint32 = 0x7B00
2270 op_SEB uint32 = 0xED0B
2271 op_SEBR uint32 = 0xB30B
2272 op_SER uint32 = 0x3B00
2273 op_SFASR uint32 = 0xB385
2274 op_SFPC uint32 = 0xB384
2275 op_SG uint32 = 0xE309
2276 op_SGF uint32 = 0xE319
2277 op_SGFR uint32 = 0xB919
2278 op_SGR uint32 = 0xB909
2279 op_SGRK uint32 = 0xB9E9
2280 op_SH uint32 = 0x4B00
2281 op_SHHHR uint32 = 0xB9C9
2282 op_SHHLR uint32 = 0xB9D9
2283 op_SHY uint32 = 0xE37B
2284 op_SIGP uint32 = 0xAE00
2285 op_SL uint32 = 0x5F00
2286 op_SLA uint32 = 0x8B00
2287 op_SLAG uint32 = 0xEB0B
2288 op_SLAK uint32 = 0xEBDD
2289 op_SLB uint32 = 0xE399
2290 op_SLBG uint32 = 0xE389
2291 op_SLBGR uint32 = 0xB989
2292 op_SLBR uint32 = 0xB999
2293 op_SLDA uint32 = 0x8F00
2294 op_SLDL uint32 = 0x8D00
2295 op_SLDT uint32 = 0xED40
2296 op_SLFI uint32 = 0xC205
2297 op_SLG uint32 = 0xE30B
2298 op_SLGF uint32 = 0xE31B
2299 op_SLGFI uint32 = 0xC204
2300 op_SLGFR uint32 = 0xB91B
2301 op_SLGR uint32 = 0xB90B
2302 op_SLGRK uint32 = 0xB9EB
2303 op_SLHHHR uint32 = 0xB9CB
2304 op_SLHHLR uint32 = 0xB9DB
2305 op_SLL uint32 = 0x8900
2306 op_SLLG uint32 = 0xEB0D
2307 op_SLLK uint32 = 0xEBDF
2308 op_SLR uint32 = 0x1F00
2309 op_SLRK uint32 = 0xB9FB
2310 op_SLXT uint32 = 0xED48
2311 op_SLY uint32 = 0xE35F
2312 op_SP uint32 = 0xFB00
2313 op_SPKA uint32 = 0xB20A
2314 op_SPM uint32 = 0x0400
2315 op_SPT uint32 = 0xB208
2316 op_SPX uint32 = 0xB210
2317 op_SQD uint32 = 0xED35
2318 op_SQDB uint32 = 0xED15
2319 op_SQDBR uint32 = 0xB315
2320 op_SQDR uint32 = 0xB244
2321 op_SQE uint32 = 0xED34
2322 op_SQEB uint32 = 0xED14
2323 op_SQEBR uint32 = 0xB314
2324 op_SQER uint32 = 0xB245
2325 op_SQXBR uint32 = 0xB316
2326 op_SQXR uint32 = 0xB336
2327 op_SR uint32 = 0x1B00
2328 op_SRA uint32 = 0x8A00
2329 op_SRAG uint32 = 0xEB0A
2330 op_SRAK uint32 = 0xEBDC
2331 op_SRDA uint32 = 0x8E00
2332 op_SRDL uint32 = 0x8C00
2333 op_SRDT uint32 = 0xED41
2334 op_SRK uint32 = 0xB9F9
2335 op_SRL uint32 = 0x8800
2336 op_SRLG uint32 = 0xEB0C
2337 op_SRLK uint32 = 0xEBDE
2338 op_SRNM uint32 = 0xB299
2339 op_SRNMB uint32 = 0xB2B8
2340 op_SRNMT uint32 = 0xB2B9
2341 op_SRP uint32 = 0xF000
2342 op_SRST uint32 = 0xB25E
2343 op_SRSTU uint32 = 0xB9BE
2344 op_SRXT uint32 = 0xED49
2345 op_SSAIR uint32 = 0xB99F
2346 op_SSAR uint32 = 0xB225
2347 op_SSCH uint32 = 0xB233
2348 op_SSKE uint32 = 0xB22B
2349 op_SSM uint32 = 0x8000
2350 op_ST uint32 = 0x5000
2351 op_STAM uint32 = 0x9B00
2352 op_STAMY uint32 = 0xEB9B
2353 op_STAP uint32 = 0xB212
2354 op_STC uint32 = 0x4200
2355 op_STCH uint32 = 0xE3C3
2356 op_STCK uint32 = 0xB205
2357 op_STCKC uint32 = 0xB207
2358 op_STCKE uint32 = 0xB278
2359 op_STCKF uint32 = 0xB27C
2360 op_STCM uint32 = 0xBE00
2361 op_STCMH uint32 = 0xEB2C
2362 op_STCMY uint32 = 0xEB2D
2363 op_STCPS uint32 = 0xB23A
2364 op_STCRW uint32 = 0xB239
2365 op_STCTG uint32 = 0xEB25
2366 op_STCTL uint32 = 0xB600
2367 op_STCY uint32 = 0xE372
2368 op_STD uint32 = 0x6000
2369 op_STDY uint32 = 0xED67
2370 op_STE uint32 = 0x7000
2371 op_STEY uint32 = 0xED66
2372 op_STFH uint32 = 0xE3CB
2373 op_STFL uint32 = 0xB2B1
2374 op_STFLE uint32 = 0xB2B0
2375 op_STFPC uint32 = 0xB29C
2376 op_STG uint32 = 0xE324
2377 op_STGRL uint32 = 0xC40B
2378 op_STH uint32 = 0x4000
2379 op_STHH uint32 = 0xE3C7
2380 op_STHRL uint32 = 0xC407
2381 op_STHY uint32 = 0xE370
2382 op_STIDP uint32 = 0xB202
2383 op_STM uint32 = 0x9000
2384 op_STMG uint32 = 0xEB24
2385 op_STMH uint32 = 0xEB26
2386 op_STMY uint32 = 0xEB90
2387 op_STNSM uint32 = 0xAC00
2388 op_STOC uint32 = 0xEBF3
2389 op_STOCG uint32 = 0xEBE3
2390 op_STOSM uint32 = 0xAD00
2391 op_STPQ uint32 = 0xE38E
2392 op_STPT uint32 = 0xB209
2393 op_STPX uint32 = 0xB211
2394 op_STRAG uint32 = 0xE502
2395 op_STRL uint32 = 0xC40F
2396 op_STRV uint32 = 0xE33E
2397 op_STRVG uint32 = 0xE32F
2398 op_STRVH uint32 = 0xE33F
2399 op_STSCH uint32 = 0xB234
2400 op_STSI uint32 = 0xB27D
2401 op_STURA uint32 = 0xB246
2402 op_STURG uint32 = 0xB925
2403 op_STY uint32 = 0xE350
2404 op_SU uint32 = 0x7F00
2405 op_SUR uint32 = 0x3F00
2406 op_SVC uint32 = 0x0A00
2407 op_SW uint32 = 0x6F00
2408 op_SWR uint32 = 0x2F00
2409 op_SXBR uint32 = 0xB34B
2410 op_SXR uint32 = 0x3700
2411 op_SXTR uint32 = 0xB3DB
2412 op_SXTRA uint32 = 0xB3DB
2413 op_SY uint32 = 0xE35B
2414 op_TABORT uint32 = 0xB2FC
2415 op_TAM uint32 = 0x010B
2416 op_TAR uint32 = 0xB24C
2417 op_TB uint32 = 0xB22C
2418 op_TBDR uint32 = 0xB351
2419 op_TBEDR uint32 = 0xB350
2420 op_TBEGIN uint32 = 0xE560
2421 op_TBEGINC uint32 = 0xE561
2422 op_TCDB uint32 = 0xED11
2423 op_TCEB uint32 = 0xED10
2424 op_TCXB uint32 = 0xED12
2425 op_TDCDT uint32 = 0xED54
2426 op_TDCET uint32 = 0xED50
2427 op_TDCXT uint32 = 0xED58
2428 op_TDGDT uint32 = 0xED55
2429 op_TDGET uint32 = 0xED51
2430 op_TDGXT uint32 = 0xED59
2431 op_TEND uint32 = 0xB2F8
2432 op_THDER uint32 = 0xB358
2433 op_THDR uint32 = 0xB359
2434 op_TM uint32 = 0x9100
2435 op_TMH uint32 = 0xA700
2436 op_TMHH uint32 = 0xA702
2437 op_TMHL uint32 = 0xA703
2438 op_TML uint32 = 0xA701
2439 op_TMLH uint32 = 0xA700
2440 op_TMLL uint32 = 0xA701
2441 op_TMY uint32 = 0xEB51
2442 op_TP uint32 = 0xEBC0
2443 op_TPI uint32 = 0xB236
2444 op_TPROT uint32 = 0xE501
2445 op_TR uint32 = 0xDC00
2446 op_TRACE uint32 = 0x9900
2447 op_TRACG uint32 = 0xEB0F
2448 op_TRAP2 uint32 = 0x01FF
2449 op_TRAP4 uint32 = 0xB2FF
2450 op_TRE uint32 = 0xB2A5
2451 op_TROO uint32 = 0xB993
2452 op_TROT uint32 = 0xB992
2453 op_TRT uint32 = 0xDD00
2454 op_TRTE uint32 = 0xB9BF
2455 op_TRTO uint32 = 0xB991
2456 op_TRTR uint32 = 0xD000
2457 op_TRTRE uint32 = 0xB9BD
2458 op_TRTT uint32 = 0xB990
2459 op_TS uint32 = 0x9300
2460 op_TSCH uint32 = 0xB235
2461 op_UNPK uint32 = 0xF300
2462 op_UNPKA uint32 = 0xEA00
2463 op_UNPKU uint32 = 0xE200
2464 op_UPT uint32 = 0x0102
2465 op_X uint32 = 0x5700
2466 op_XC uint32 = 0xD700
2467 op_XG uint32 = 0xE382
2468 op_XGR uint32 = 0xB982
2469 op_XGRK uint32 = 0xB9E7
2470 op_XI uint32 = 0x9700
2471 op_XIHF uint32 = 0xC006
2472 op_XILF uint32 = 0xC007
2473 op_XIY uint32 = 0xEB57
2474 op_XR uint32 = 0x1700
2475 op_XRK uint32 = 0xB9F7
2476 op_XSCH uint32 = 0xB276
2477 op_XY uint32 = 0xE357
2478 op_ZAP uint32 = 0xF800
2479 op_BRRK uint32 = 0x0001
2480
2481
2482 op_CXPT uint32 = 0xEDAF
2483 op_CDPT uint32 = 0xEDAE
2484 op_CPXT uint32 = 0xEDAD
2485 op_CPDT uint32 = 0xEDAC
2486 op_LZRF uint32 = 0xE33B
2487 op_LZRG uint32 = 0xE32A
2488 op_LCCB uint32 = 0xE727
2489 op_LOCHHI uint32 = 0xEC4E
2490 op_LOCHI uint32 = 0xEC42
2491 op_LOCGHI uint32 = 0xEC46
2492 op_LOCFH uint32 = 0xEBE0
2493 op_LOCFHR uint32 = 0xB9E0
2494 op_LLZRGF uint32 = 0xE33A
2495 op_STOCFH uint32 = 0xEBE1
2496 op_VA uint32 = 0xE7F3
2497 op_VACC uint32 = 0xE7F1
2498 op_VAC uint32 = 0xE7BB
2499 op_VACCC uint32 = 0xE7B9
2500 op_VN uint32 = 0xE768
2501 op_VNC uint32 = 0xE769
2502 op_VAVG uint32 = 0xE7F2
2503 op_VAVGL uint32 = 0xE7F0
2504 op_VCKSM uint32 = 0xE766
2505 op_VCEQ uint32 = 0xE7F8
2506 op_VCH uint32 = 0xE7FB
2507 op_VCHL uint32 = 0xE7F9
2508 op_VCLZ uint32 = 0xE753
2509 op_VCTZ uint32 = 0xE752
2510 op_VEC uint32 = 0xE7DB
2511 op_VECL uint32 = 0xE7D9
2512 op_VERIM uint32 = 0xE772
2513 op_VERLL uint32 = 0xE733
2514 op_VERLLV uint32 = 0xE773
2515 op_VESLV uint32 = 0xE770
2516 op_VESL uint32 = 0xE730
2517 op_VESRA uint32 = 0xE73A
2518 op_VESRAV uint32 = 0xE77A
2519 op_VESRL uint32 = 0xE738
2520 op_VESRLV uint32 = 0xE778
2521 op_VX uint32 = 0xE76D
2522 op_VFAE uint32 = 0xE782
2523 op_VFEE uint32 = 0xE780
2524 op_VFENE uint32 = 0xE781
2525 op_VFA uint32 = 0xE7E3
2526 op_WFK uint32 = 0xE7CA
2527 op_VFCE uint32 = 0xE7E8
2528 op_VFCH uint32 = 0xE7EB
2529 op_VFCHE uint32 = 0xE7EA
2530 op_WFC uint32 = 0xE7CB
2531 op_VCDG uint32 = 0xE7C3
2532 op_VCDLG uint32 = 0xE7C1
2533 op_VCGD uint32 = 0xE7C2
2534 op_VCLGD uint32 = 0xE7C0
2535 op_VFD uint32 = 0xE7E5
2536 op_VLDE uint32 = 0xE7C4
2537 op_VLED uint32 = 0xE7C5
2538 op_VFM uint32 = 0xE7E7
2539 op_VFMA uint32 = 0xE78F
2540 op_VFMS uint32 = 0xE78E
2541 op_VFPSO uint32 = 0xE7CC
2542 op_VFSQ uint32 = 0xE7CE
2543 op_VFS uint32 = 0xE7E2
2544 op_VFTCI uint32 = 0xE74A
2545 op_VGFM uint32 = 0xE7B4
2546 op_VGFMA uint32 = 0xE7BC
2547 op_VGEF uint32 = 0xE713
2548 op_VGEG uint32 = 0xE712
2549 op_VGBM uint32 = 0xE744
2550 op_VGM uint32 = 0xE746
2551 op_VISTR uint32 = 0xE75C
2552 op_VL uint32 = 0xE706
2553 op_VLR uint32 = 0xE756
2554 op_VLREP uint32 = 0xE705
2555 op_VLC uint32 = 0xE7DE
2556 op_VLEH uint32 = 0xE701
2557 op_VLEF uint32 = 0xE703
2558 op_VLEG uint32 = 0xE702
2559 op_VLEB uint32 = 0xE700
2560 op_VLEIH uint32 = 0xE741
2561 op_VLEIF uint32 = 0xE743
2562 op_VLEIG uint32 = 0xE742
2563 op_VLEIB uint32 = 0xE740
2564 op_VFI uint32 = 0xE7C7
2565 op_VLGV uint32 = 0xE721
2566 op_VLLEZ uint32 = 0xE704
2567 op_VLM uint32 = 0xE736
2568 op_VLP uint32 = 0xE7DF
2569 op_VLBB uint32 = 0xE707
2570 op_VLVG uint32 = 0xE722
2571 op_VLVGP uint32 = 0xE762
2572 op_VLL uint32 = 0xE737
2573 op_VMX uint32 = 0xE7FF
2574 op_VMXL uint32 = 0xE7FD
2575 op_VMRH uint32 = 0xE761
2576 op_VMRL uint32 = 0xE760
2577 op_VMN uint32 = 0xE7FE
2578 op_VMNL uint32 = 0xE7FC
2579 op_VMAE uint32 = 0xE7AE
2580 op_VMAH uint32 = 0xE7AB
2581 op_VMALE uint32 = 0xE7AC
2582 op_VMALH uint32 = 0xE7A9
2583 op_VMALO uint32 = 0xE7AD
2584 op_VMAL uint32 = 0xE7AA
2585 op_VMAO uint32 = 0xE7AF
2586 op_VME uint32 = 0xE7A6
2587 op_VMH uint32 = 0xE7A3
2588 op_VMLE uint32 = 0xE7A4
2589 op_VMLH uint32 = 0xE7A1
2590 op_VMLO uint32 = 0xE7A5
2591 op_VML uint32 = 0xE7A2
2592 op_VMO uint32 = 0xE7A7
2593 op_VNO uint32 = 0xE76B
2594 op_VO uint32 = 0xE76A
2595 op_VPK uint32 = 0xE794
2596 op_VPKLS uint32 = 0xE795
2597 op_VPKS uint32 = 0xE797
2598 op_VPERM uint32 = 0xE78C
2599 op_VPDI uint32 = 0xE784
2600 op_VPOPCT uint32 = 0xE750
2601 op_VREP uint32 = 0xE74D
2602 op_VREPI uint32 = 0xE745
2603 op_VSCEF uint32 = 0xE71B
2604 op_VSCEG uint32 = 0xE71A
2605 op_VSEL uint32 = 0xE78D
2606 op_VSL uint32 = 0xE774
2607 op_VSLB uint32 = 0xE775
2608 op_VSLDB uint32 = 0xE777
2609 op_VSRA uint32 = 0xE77E
2610 op_VSRAB uint32 = 0xE77F
2611 op_VSRL uint32 = 0xE77C
2612 op_VSRLB uint32 = 0xE77D
2613 op_VSEG uint32 = 0xE75F
2614 op_VST uint32 = 0xE70E
2615 op_VSTEH uint32 = 0xE709
2616 op_VSTEF uint32 = 0xE70B
2617 op_VSTEG uint32 = 0xE70A
2618 op_VSTEB uint32 = 0xE708
2619 op_VSTM uint32 = 0xE73E
2620 op_VSTL uint32 = 0xE73F
2621 op_VSTRC uint32 = 0xE78A
2622 op_VS uint32 = 0xE7F7
2623 op_VSCBI uint32 = 0xE7F5
2624 op_VSBCBI uint32 = 0xE7BD
2625 op_VSBI uint32 = 0xE7BF
2626 op_VSUMG uint32 = 0xE765
2627 op_VSUMQ uint32 = 0xE767
2628 op_VSUM uint32 = 0xE764
2629 op_VTM uint32 = 0xE7D8
2630 op_VUPH uint32 = 0xE7D7
2631 op_VUPLH uint32 = 0xE7D5
2632 op_VUPLL uint32 = 0xE7D4
2633 op_VUPL uint32 = 0xE7D6
2634 op_VMSL uint32 = 0xE7B8
2635
2636
2637 op_KDSA uint32 = 0xB93A
2638
2639 )
2640
2641 func oclass(a *obj.Addr) int {
2642 return int(a.Class) - 1
2643 }
2644
2645
2646
2647 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) {
2648 if sym == nil {
2649 c.ctxt.Diag("require symbol to apply relocation")
2650 }
2651 offset := int64(2)
2652 c.cursym.AddRel(c.ctxt, obj.Reloc{
2653 Type: objabi.R_PCRELDBL,
2654 Off: int32(c.pc + offset),
2655 Siz: 4,
2656 Sym: sym,
2657 Add: add + offset + 4,
2658 })
2659 }
2660
2661 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) {
2662 if sym == nil {
2663 c.ctxt.Diag("require symbol to apply relocation")
2664 }
2665 offset += int64(2)
2666 c.cursym.AddRel(c.ctxt, obj.Reloc{
2667 Type: objabi.R_PCRELDBL,
2668 Off: int32(c.pc + offset),
2669 Siz: 4,
2670 Sym: sym,
2671 Add: add + offset + 4,
2672 })
2673 }
2674
2675
2676
2677 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) {
2678 if sym == nil {
2679 c.ctxt.Diag("require symbol to apply relocation")
2680 }
2681 offset := int64(2)
2682 c.cursym.AddRel(c.ctxt, obj.Reloc{
2683 Type: objabi.R_CALL,
2684 Off: int32(c.pc + offset),
2685 Siz: 4,
2686 Sym: sym,
2687 Add: add + offset + int64(4),
2688 })
2689 }
2690
2691 func (c *ctxtz) branchMask(p *obj.Prog) CCMask {
2692 switch p.As {
2693 case ABRC, ALOCR, ALOCGR,
2694 ACRJ, ACGRJ, ACIJ, ACGIJ,
2695 ACLRJ, ACLGRJ, ACLIJ, ACLGIJ:
2696 return CCMask(p.From.Offset)
2697 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2698 return Equal
2699 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2700 return GreaterOrEqual
2701 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2702 return Greater
2703 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2704 return LessOrEqual
2705 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2706 return Less
2707 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2708 return NotEqual
2709 case ABLEU:
2710 return NotGreater
2711 case ABLTU:
2712 return LessOrUnordered
2713 case ABVC:
2714 return Never
2715 case ABVS:
2716 return Unordered
2717 }
2718 c.ctxt.Diag("unknown conditional branch %v", p.As)
2719 return Always
2720 }
2721
2722 func regtmp(p *obj.Prog) uint32 {
2723 p.Mark |= USETMP
2724 return REGTMP
2725 }
2726
2727 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2728 o := c.oplook(p)
2729
2730 if o == nil {
2731 return
2732 }
2733
2734
2735
2736
2737 switch o.i {
2738 default:
2739 c.ctxt.Diag("unknown index %d", o.i)
2740
2741 case 0:
2742 break
2743
2744 case 1:
2745 switch p.As {
2746 default:
2747 c.ctxt.Diag("unhandled operation: %v", p.As)
2748 case AMOVD:
2749 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2750
2751 case AMOVW:
2752 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2753 case AMOVH:
2754 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2755 case AMOVB:
2756 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2757
2758 case AMOVWZ:
2759 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2760 case AMOVHZ:
2761 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2762 case AMOVBZ:
2763 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2764
2765 case AMOVDBR:
2766 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2767 case AMOVWBR:
2768 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2769
2770 case AFMOVD, AFMOVS:
2771 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2772 }
2773
2774 case 2:
2775 r := p.Reg
2776 if r == 0 {
2777 r = p.To.Reg
2778 }
2779
2780 var opcode uint32
2781
2782 switch p.As {
2783 default:
2784 c.ctxt.Diag("invalid opcode")
2785 case AADD:
2786 opcode = op_AGRK
2787 case AADDC:
2788 opcode = op_ALGRK
2789 case AADDE:
2790 opcode = op_ALCGR
2791 case AADDW:
2792 opcode = op_ARK
2793 case AMULLW:
2794 opcode = op_MSGFR
2795 case AMULLD:
2796 opcode = op_MSGR
2797 case ADIVW, AMODW:
2798 opcode = op_DSGFR
2799 case ADIVWU, AMODWU:
2800 opcode = op_DLR
2801 case ADIVD, AMODD:
2802 opcode = op_DSGR
2803 case ADIVDU, AMODDU:
2804 opcode = op_DLGR
2805 }
2806
2807 switch p.As {
2808 default:
2809
2810 case AADD, AADDC, AADDW:
2811 if p.As == AADDW && r == p.To.Reg {
2812 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2813 } else {
2814 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2815 }
2816
2817 case AADDE, AMULLW, AMULLD:
2818 if r == p.To.Reg {
2819 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2820 } else if p.From.Reg == p.To.Reg {
2821 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2822 } else {
2823 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2824 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2825 }
2826
2827 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2828 if p.As == ADIVWU || p.As == ADIVDU {
2829 zRI(op_LGHI, regtmp(p), 0, asm)
2830 }
2831 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2832 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2833 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2834
2835 case AMODW, AMODWU, AMODD, AMODDU:
2836 if p.As == AMODWU || p.As == AMODDU {
2837 zRI(op_LGHI, regtmp(p), 0, asm)
2838 }
2839 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2840 zRRE(opcode, regtmp(p), uint32(p.From.Reg), asm)
2841 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2842
2843 }
2844
2845 case 3:
2846 v := c.vregoff(&p.From)
2847 switch p.As {
2848 case AMOVBZ:
2849 v = int64(uint8(v))
2850 case AMOVHZ:
2851 v = int64(uint16(v))
2852 case AMOVWZ:
2853 v = int64(uint32(v))
2854 case AMOVB:
2855 v = int64(int8(v))
2856 case AMOVH:
2857 v = int64(int16(v))
2858 case AMOVW:
2859 v = int64(int32(v))
2860 }
2861 if int64(int16(v)) == v {
2862 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2863 } else if v&0xffff0000 == v {
2864 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2865 } else if v&0xffff00000000 == v {
2866 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2867 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2868 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2869 } else if int64(int32(v)) == v {
2870 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2871 } else if int64(uint32(v)) == v {
2872 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2873 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2874 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2875 } else {
2876 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2877 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2878 }
2879
2880 case 4:
2881 r := p.Reg
2882 if r == 0 {
2883 r = p.To.Reg
2884 }
2885 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2886 zRRE(op_MLGR, regtmp(p), uint32(p.From.Reg), asm)
2887 switch p.As {
2888 case AMULHDU:
2889
2890 zRRE(op_LGR, uint32(p.To.Reg), regtmp(p), asm)
2891 case AMULHD:
2892
2893
2894 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2895 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2896 zRRE(op_SGR, regtmp(p), REGTMP2, asm)
2897 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2898 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2899 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), regtmp(p), asm)
2900 }
2901
2902 case 5:
2903 zI(op_SVC, 0, asm)
2904
2905 case 6:
2906 var oprr, oprre, oprrf uint32
2907 switch p.As {
2908 case AAND:
2909 oprre = op_NGR
2910 oprrf = op_NGRK
2911 case AANDW:
2912 oprr = op_NR
2913 oprrf = op_NRK
2914 case AOR:
2915 oprre = op_OGR
2916 oprrf = op_OGRK
2917 case AORW:
2918 oprr = op_OR
2919 oprrf = op_ORK
2920 case AXOR:
2921 oprre = op_XGR
2922 oprrf = op_XGRK
2923 case AXORW:
2924 oprr = op_XR
2925 oprrf = op_XRK
2926 }
2927 if p.Reg == 0 {
2928 if oprr != 0 {
2929 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2930 } else {
2931 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2932 }
2933 } else {
2934 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2935 }
2936
2937 case 7:
2938 d2 := c.vregoff(&p.From)
2939 b2 := p.From.Reg
2940 r3 := p.Reg
2941 if r3 == 0 {
2942 r3 = p.To.Reg
2943 }
2944 r1 := p.To.Reg
2945 var opcode uint32
2946 switch p.As {
2947 default:
2948 case ASLD:
2949 opcode = op_SLLG
2950 case ASRD:
2951 opcode = op_SRLG
2952 case ASLW:
2953 opcode = op_SLLK
2954 case ASRW:
2955 opcode = op_SRLK
2956 case ARLL:
2957 opcode = op_RLL
2958 case ARLLG:
2959 opcode = op_RLLG
2960 case ASRAW:
2961 opcode = op_SRAK
2962 case ASRAD:
2963 opcode = op_SRAG
2964 }
2965 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2966
2967 case 8:
2968 if p.To.Reg&1 != 0 {
2969 c.ctxt.Diag("target must be an even-numbered register")
2970 }
2971
2972 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2973
2974 case 9:
2975 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2976
2977 case 10:
2978 r := int(p.Reg)
2979
2980 switch p.As {
2981 default:
2982 case ASUB:
2983 if r == 0 {
2984 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2985 } else {
2986 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2987 }
2988 case ASUBC:
2989 if r == 0 {
2990 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2991 } else {
2992 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2993 }
2994 case ASUBE:
2995 if r == 0 {
2996 r = int(p.To.Reg)
2997 }
2998 if r == int(p.To.Reg) {
2999 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3000 } else if p.From.Reg == p.To.Reg {
3001 zRRE(op_LGR, regtmp(p), uint32(p.From.Reg), asm)
3002 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3003 zRRE(op_SLBGR, uint32(p.To.Reg), regtmp(p), asm)
3004 } else {
3005 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3006 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3007 }
3008 case ASUBW:
3009 if r == 0 {
3010 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3011 } else {
3012 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
3013 }
3014 }
3015
3016 case 11:
3017 v := int32(0)
3018
3019 if p.To.Target() != nil {
3020 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3021 }
3022
3023 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
3024 zRI(op_BRC, 0xF, uint32(v), asm)
3025 } else {
3026 if p.As == ABL {
3027 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
3028 } else {
3029 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
3030 }
3031 if p.To.Sym != nil {
3032 c.addcallreloc(p.To.Sym, p.To.Offset)
3033 }
3034 }
3035
3036 case 12:
3037 r1 := p.To.Reg
3038 d2 := c.vregoff(&p.From)
3039 b2 := p.From.Reg
3040 if b2 == 0 {
3041 b2 = REGSP
3042 }
3043 x2 := p.From.Index
3044 if -DISP20/2 > d2 || d2 >= DISP20/2 {
3045 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3046 if x2 != 0 {
3047 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3048 }
3049 x2 = int16(regtmp(p))
3050 d2 = 0
3051 }
3052 var opx, opxy uint32
3053 switch p.As {
3054 case AADD:
3055 opxy = op_AG
3056 case AADDC:
3057 opxy = op_ALG
3058 case AADDE:
3059 opxy = op_ALCG
3060 case AADDW:
3061 opx = op_A
3062 opxy = op_AY
3063 case AMULLW:
3064 opx = op_MS
3065 opxy = op_MSY
3066 case AMULLD:
3067 opxy = op_MSG
3068 case ASUB:
3069 opxy = op_SG
3070 case ASUBC:
3071 opxy = op_SLG
3072 case ASUBE:
3073 opxy = op_SLBG
3074 case ASUBW:
3075 opx = op_S
3076 opxy = op_SY
3077 case AAND:
3078 opxy = op_NG
3079 case AANDW:
3080 opx = op_N
3081 opxy = op_NY
3082 case AOR:
3083 opxy = op_OG
3084 case AORW:
3085 opx = op_O
3086 opxy = op_OY
3087 case AXOR:
3088 opxy = op_XG
3089 case AXORW:
3090 opx = op_X
3091 opxy = op_XY
3092 }
3093 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3094 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3095 } else {
3096 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3097 }
3098
3099 case 13:
3100 r1 := p.To.Reg
3101 r2 := p.RestArgs[2].Reg
3102 i3 := uint8(p.From.Offset)
3103 i4 := uint8(p.RestArgs[0].Offset)
3104 i5 := uint8(p.RestArgs[1].Offset)
3105 switch p.As {
3106 case ARNSBGT, ARXSBGT, AROSBGT:
3107 i3 |= 0x80
3108 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3109 i4 |= 0x80
3110 }
3111 var opcode uint32
3112 switch p.As {
3113 case ARNSBG, ARNSBGT:
3114 opcode = op_RNSBG
3115 case ARXSBG, ARXSBGT:
3116 opcode = op_RXSBG
3117 case AROSBG, AROSBGT:
3118 opcode = op_ROSBG
3119 case ARISBG, ARISBGZ:
3120 opcode = op_RISBG
3121 case ARISBGN, ARISBGNZ:
3122 opcode = op_RISBGN
3123 case ARISBHG, ARISBHGZ:
3124 opcode = op_RISBHG
3125 case ARISBLG, ARISBLGZ:
3126 opcode = op_RISBLG
3127 }
3128 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3129
3130 case 15:
3131 r := p.To.Reg
3132 if p.As == ABCL || p.As == ABL {
3133 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3134 } else {
3135 zRR(op_BCR, uint32(Always), uint32(r), asm)
3136 }
3137
3138 case 16:
3139 v := int32(0)
3140 if p.To.Target() != nil {
3141 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3142 }
3143 mask := uint32(c.branchMask(p))
3144 if p.To.Sym == nil && int32(int16(v)) == v {
3145 zRI(op_BRC, mask, uint32(v), asm)
3146 } else {
3147 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3148 }
3149 if p.To.Sym != nil {
3150 c.addrilreloc(p.To.Sym, p.To.Offset)
3151 }
3152
3153 case 17:
3154 m3 := uint32(c.branchMask(p))
3155 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3156
3157 case 18:
3158 if p.As == ABL {
3159 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3160 } else {
3161 zRR(op_BCR, uint32(Always), uint32(p.To.Reg), asm)
3162 }
3163
3164 case 19:
3165 d := c.vregoff(&p.From)
3166 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3167 if d&1 != 0 {
3168 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3169 d -= 1
3170 }
3171 c.addrilreloc(p.From.Sym, d)
3172
3173 case 21:
3174 v := c.vregoff(&p.From)
3175 r := p.Reg
3176 if r == 0 {
3177 r = p.To.Reg
3178 }
3179 switch p.As {
3180 case ASUB:
3181 zRIL(_a, op_LGFI, uint32(regtmp(p)), uint32(v), asm)
3182 zRRF(op_SLGRK, uint32(regtmp(p)), 0, uint32(p.To.Reg), uint32(r), asm)
3183 case ASUBC:
3184 if r != p.To.Reg {
3185 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3186 }
3187 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3188 case ASUBW:
3189 if r != p.To.Reg {
3190 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3191 }
3192 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3193 }
3194
3195 case 22:
3196 v := c.vregoff(&p.From)
3197 r := p.Reg
3198 if r == 0 {
3199 r = p.To.Reg
3200 }
3201 var opri, opril, oprie uint32
3202 switch p.As {
3203 case AADD:
3204 opri = op_AGHI
3205 opril = op_AGFI
3206 oprie = op_AGHIK
3207 case AADDC:
3208 opril = op_ALGFI
3209 oprie = op_ALGHSIK
3210 case AADDW:
3211 opri = op_AHI
3212 opril = op_AFI
3213 oprie = op_AHIK
3214 case AMULLW:
3215 opri = op_MHI
3216 opril = op_MSFI
3217 case AMULLD:
3218 opri = op_MGHI
3219 opril = op_MSGFI
3220 }
3221 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3222 switch p.As {
3223 case AADD, AADDC, AMULLD:
3224 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3225 case AADDW, AMULLW:
3226 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3227 }
3228 r = p.To.Reg
3229 }
3230 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3231 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3232 } else if oprie != 0 && int64(int16(v)) == v {
3233 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3234 } else {
3235 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3236 }
3237
3238 case 23:
3239
3240 v := c.vregoff(&p.From)
3241 switch p.As {
3242 default:
3243 c.ctxt.Diag("%v is not supported", p)
3244 case AAND:
3245 if v >= 0 {
3246 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3247 zRRE(op_NGR, uint32(p.To.Reg), regtmp(p), asm)
3248 } else if int64(int16(v)) == v {
3249 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3250 } else {
3251 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3252 }
3253 case AOR:
3254 if int64(uint32(v)) != v {
3255 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3256 zRRE(op_OGR, uint32(p.To.Reg), regtmp(p), asm)
3257 } else if int64(uint16(v)) == v {
3258 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3259 } else {
3260 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3261 }
3262 case AXOR:
3263 if int64(uint32(v)) != v {
3264 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3265 zRRE(op_XGR, uint32(p.To.Reg), regtmp(p), asm)
3266 } else {
3267 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3268 }
3269 }
3270
3271 case 24:
3272 v := c.vregoff(&p.From)
3273 switch p.As {
3274 case AANDW:
3275 if uint32(v&0xffff0000) == 0xffff0000 {
3276 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3277 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3278 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3279 } else {
3280 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3281 }
3282 case AORW:
3283 if uint32(v&0xffff0000) == 0 {
3284 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3285 } else if uint32(v&0x0000ffff) == 0 {
3286 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3287 } else {
3288 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3289 }
3290 case AXORW:
3291 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3292 }
3293
3294 case 25:
3295 m3 := uint32(c.branchMask(p))
3296 var opcode uint32
3297 switch p.As {
3298 case ALOCR:
3299 opcode = op_LOCR
3300 case ALOCGR:
3301 opcode = op_LOCGR
3302 }
3303 zRRF(opcode, m3, 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3304
3305 case 26:
3306 v := c.regoff(&p.From)
3307 r := p.From.Reg
3308 if r == 0 {
3309 r = REGSP
3310 }
3311 i := p.From.Index
3312 if v >= 0 && v < DISP12 {
3313 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3314 } else if v >= -DISP20/2 && v < DISP20/2 {
3315 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3316 } else {
3317 zRIL(_a, op_LGFI, regtmp(p), uint32(v), asm)
3318 zRX(op_LA, uint32(p.To.Reg), uint32(r), regtmp(p), uint32(i), asm)
3319 }
3320
3321 case 31:
3322 wd := uint64(c.vregoff(&p.From))
3323 *asm = append(*asm,
3324 uint8(wd>>56),
3325 uint8(wd>>48),
3326 uint8(wd>>40),
3327 uint8(wd>>32),
3328 uint8(wd>>24),
3329 uint8(wd>>16),
3330 uint8(wd>>8),
3331 uint8(wd))
3332
3333 case 32:
3334 var opcode uint32
3335 switch p.As {
3336 default:
3337 c.ctxt.Diag("invalid opcode")
3338 case AFADD:
3339 opcode = op_ADBR
3340 case AFADDS:
3341 opcode = op_AEBR
3342 case AFDIV:
3343 opcode = op_DDBR
3344 case AFDIVS:
3345 opcode = op_DEBR
3346 case AFMUL:
3347 opcode = op_MDBR
3348 case AFMULS:
3349 opcode = op_MEEBR
3350 case AFSUB:
3351 opcode = op_SDBR
3352 case AFSUBS:
3353 opcode = op_SEBR
3354 }
3355 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3356
3357 case 33:
3358 r := p.From.Reg
3359 if oclass(&p.From) == C_NONE {
3360 r = p.To.Reg
3361 }
3362 var opcode uint32
3363 switch p.As {
3364 default:
3365 case AFABS:
3366 opcode = op_LPDBR
3367 case AFNABS:
3368 opcode = op_LNDBR
3369 case ALPDFR:
3370 opcode = op_LPDFR
3371 case ALNDFR:
3372 opcode = op_LNDFR
3373 case AFNEG:
3374 opcode = op_LCDFR
3375 case AFNEGS:
3376 opcode = op_LCEBR
3377 case ALCDBR:
3378 opcode = op_LCDBR
3379 case ALEDBR:
3380 opcode = op_LEDBR
3381 case ALDEBR:
3382 opcode = op_LDEBR
3383 case AFSQRT:
3384 opcode = op_SQDBR
3385 case AFSQRTS:
3386 opcode = op_SQEBR
3387 }
3388 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3389
3390 case 34:
3391 var opcode uint32
3392 switch p.As {
3393 default:
3394 c.ctxt.Diag("invalid opcode")
3395 case AFMADD:
3396 opcode = op_MADBR
3397 case AFMADDS:
3398 opcode = op_MAEBR
3399 case AFMSUB:
3400 opcode = op_MSDBR
3401 case AFMSUBS:
3402 opcode = op_MSEBR
3403 }
3404 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3405
3406 case 35:
3407 d2 := c.regoff(&p.To)
3408 b2 := p.To.Reg
3409 if b2 == 0 {
3410 b2 = REGSP
3411 }
3412 x2 := p.To.Index
3413 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3414 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3415 if x2 != 0 {
3416 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3417 }
3418 x2 = int16(regtmp(p))
3419 d2 = 0
3420 }
3421
3422 if op, ok := c.zopstore12(p.As); ok && isU12(d2) {
3423 zRX(op, uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3424 } else {
3425 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3426 }
3427
3428 case 36:
3429 d2 := c.regoff(&p.From)
3430 b2 := p.From.Reg
3431 if b2 == 0 {
3432 b2 = REGSP
3433 }
3434 x2 := p.From.Index
3435 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3436 zRIL(_a, op_LGFI, regtmp(p), uint32(d2), asm)
3437 if x2 != 0 {
3438 zRX(op_LA, regtmp(p), regtmp(p), uint32(x2), 0, asm)
3439 }
3440 x2 = int16(regtmp(p))
3441 d2 = 0
3442 }
3443
3444 if op, ok := c.zopload12(p.As); ok && isU12(d2) {
3445 zRX(op, uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3446 } else {
3447 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3448 }
3449
3450 case 40:
3451 wd := uint32(c.regoff(&p.From))
3452 if p.As == AWORD {
3453 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3454 } else {
3455 *asm = append(*asm, uint8(wd))
3456 }
3457
3458 case 41:
3459 r1 := p.From.Reg
3460 ri2 := (p.To.Target().Pc - p.Pc) >> 1
3461 if int64(int16(ri2)) != ri2 {
3462 c.ctxt.Diag("branch target too far away")
3463 }
3464 var opcode uint32
3465 switch p.As {
3466 case ABRCT:
3467 opcode = op_BRCT
3468 case ABRCTG:
3469 opcode = op_BRCTG
3470 }
3471 zRI(opcode, uint32(r1), uint32(ri2), asm)
3472
3473 case 47:
3474 r := p.From.Reg
3475 if r == 0 {
3476 r = p.To.Reg
3477 }
3478 switch p.As {
3479 case ANEG:
3480 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3481 case ANEGW:
3482 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3483 }
3484
3485 case 48:
3486 m3 := c.vregoff(&p.From)
3487 if 0 > m3 || m3 > 7 {
3488 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3489 }
3490 var opcode uint32
3491 switch p.As {
3492 case AFIEBR:
3493 opcode = op_FIEBR
3494 case AFIDBR:
3495 opcode = op_FIDBR
3496 }
3497 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3498
3499 case 49:
3500 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3501
3502 case 50:
3503 var opcode uint32
3504 switch p.As {
3505 case ALTEBR:
3506 opcode = op_LTEBR
3507 case ALTDBR:
3508 opcode = op_LTDBR
3509 }
3510 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3511
3512 case 51:
3513 var opcode uint32
3514 switch p.As {
3515 case ATCEB:
3516 opcode = op_TCEB
3517 case ATCDB:
3518 opcode = op_TCDB
3519 }
3520 d2 := c.regoff(&p.To)
3521 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3522
3523 case 62:
3524 zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3525
3526 case 66:
3527 zRR(op_BCR, uint32(Never), 0, asm)
3528
3529 case 67:
3530 var opcode uint32
3531 switch p.As {
3532 case AFMOVS:
3533 opcode = op_LZER
3534 case AFMOVD:
3535 opcode = op_LZDR
3536 }
3537 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3538
3539 case 68:
3540 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3541
3542 case 69:
3543 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3544
3545 case 70:
3546 if p.As == ACMPW || p.As == ACMPWU {
3547 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3548 } else {
3549 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3550 }
3551
3552 case 71:
3553 v := c.vregoff(&p.To)
3554 switch p.As {
3555 case ACMP, ACMPW:
3556 if int64(int32(v)) != v {
3557 c.ctxt.Diag("%v overflows an int32", v)
3558 }
3559 case ACMPU, ACMPWU:
3560 if int64(uint32(v)) != v {
3561 c.ctxt.Diag("%v overflows a uint32", v)
3562 }
3563 }
3564 if p.As == ACMP && int64(int16(v)) == v {
3565 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3566 } else if p.As == ACMPW && int64(int16(v)) == v {
3567 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3568 } else {
3569 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3570 }
3571
3572 case 72:
3573 v := c.regoff(&p.From)
3574 d := c.regoff(&p.To)
3575 r := p.To.Reg
3576 if p.To.Index != 0 {
3577 c.ctxt.Diag("cannot use index register")
3578 }
3579 if r == 0 {
3580 r = REGSP
3581 }
3582 var opcode uint32
3583 switch p.As {
3584 case AMOVD:
3585 opcode = op_MVGHI
3586 case AMOVW, AMOVWZ:
3587 opcode = op_MVHI
3588 case AMOVH, AMOVHZ:
3589 opcode = op_MVHHI
3590 case AMOVB, AMOVBZ:
3591 opcode = op_MVI
3592 }
3593 if d < 0 || d >= DISP12 {
3594 if r == int16(regtmp(p)) {
3595 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3596 }
3597 if d >= -DISP20/2 && d < DISP20/2 {
3598 if opcode == op_MVI {
3599 opcode = op_MVIY
3600 } else {
3601 zRXY(op_LAY, uint32(regtmp(p)), 0, uint32(r), uint32(d), asm)
3602 r = int16(regtmp(p))
3603 d = 0
3604 }
3605 } else {
3606 zRIL(_a, op_LGFI, regtmp(p), uint32(d), asm)
3607 zRX(op_LA, regtmp(p), regtmp(p), uint32(r), 0, asm)
3608 r = int16(regtmp(p))
3609 d = 0
3610 }
3611 }
3612 switch opcode {
3613 case op_MVI:
3614 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3615 case op_MVIY:
3616 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3617 default:
3618 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3619 }
3620
3621 case 73:
3622 zE(op_BRRK, asm)
3623
3624 case 74:
3625 i2 := c.regoff(&p.To)
3626 switch p.As {
3627 case AMOVD:
3628 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3629 case AMOVW, AMOVWZ:
3630 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3631 case AMOVH, AMOVHZ:
3632 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3633 case AMOVB, AMOVBZ:
3634 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3635 adj := uint32(0)
3636 if i2&1 != 0 {
3637 i2 -= 1
3638 adj = 1
3639 }
3640 zRX(op_STC, uint32(p.From.Reg), 0, regtmp(p), adj, asm)
3641 case AFMOVD:
3642 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3643 zRX(op_STD, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3644 case AFMOVS:
3645 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3646 zRX(op_STE, uint32(p.From.Reg), 0, regtmp(p), 0, asm)
3647 }
3648 c.addrilreloc(p.To.Sym, int64(i2))
3649
3650 case 75:
3651 i2 := c.regoff(&p.From)
3652 switch p.As {
3653 case AMOVD:
3654 if i2&1 != 0 {
3655 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3656 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 1, asm)
3657 i2 -= 1
3658 } else {
3659 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3660 }
3661 case AMOVW:
3662 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3663 case AMOVWZ:
3664 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3665 case AMOVH:
3666 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3667 case AMOVHZ:
3668 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3669 case AMOVB, AMOVBZ:
3670 zRIL(_b, op_LARL, regtmp(p), 0, asm)
3671 adj := uint32(0)
3672 if i2&1 != 0 {
3673 i2 -= 1
3674 adj = 1
3675 }
3676 switch p.As {
3677 case AMOVB:
3678 zRXY(op_LGB, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3679 case AMOVBZ:
3680 zRXY(op_LLGC, uint32(p.To.Reg), 0, regtmp(p), adj, asm)
3681 }
3682 case AFMOVD:
3683 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3684 zRX(op_LD, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3685 case AFMOVS:
3686 zRIL(_a, op_LARL, regtmp(p), 0, asm)
3687 zRX(op_LE, uint32(p.To.Reg), 0, regtmp(p), 0, asm)
3688 }
3689 c.addrilreloc(p.From.Sym, int64(i2))
3690
3691 case 76:
3692 zRR(op_SPM, uint32(p.From.Reg), 0, asm)
3693
3694 case 77:
3695 if p.From.Offset > 255 || p.From.Offset < 1 {
3696 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3697 zE(op_TRAP2, asm)
3698 } else {
3699 zI(op_SVC, uint32(p.From.Offset), asm)
3700 }
3701
3702 case 78:
3703
3704
3705 *asm = append(*asm, 0, 0, 0, 0)
3706
3707 case 79:
3708 v := c.regoff(&p.To)
3709 if v < 0 {
3710 v = 0
3711 }
3712 if p.As == ACS {
3713 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3714 } else if p.As == ACSG {
3715 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3716 }
3717
3718 case 80:
3719 zRR(op_BCR, 14, 0, asm)
3720
3721 case 81:
3722 switch p.As {
3723 case ALDGR:
3724 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3725 case ALGDR:
3726 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3727 }
3728
3729 case 82:
3730 var opcode uint32
3731 switch p.As {
3732 default:
3733 log.Fatalf("unexpected opcode %v", p.As)
3734 case ACEFBRA:
3735 opcode = op_CEFBRA
3736 case ACDFBRA:
3737 opcode = op_CDFBRA
3738 case ACEGBRA:
3739 opcode = op_CEGBRA
3740 case ACDGBRA:
3741 opcode = op_CDGBRA
3742 case ACELFBR:
3743 opcode = op_CELFBR
3744 case ACDLFBR:
3745 opcode = op_CDLFBR
3746 case ACELGBR:
3747 opcode = op_CELGBR
3748 case ACDLGBR:
3749 opcode = op_CDLGBR
3750 }
3751
3752
3753
3754
3755 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3756
3757 case 83:
3758 var opcode uint32
3759 switch p.As {
3760 default:
3761 log.Fatalf("unexpected opcode %v", p.As)
3762 case ACFEBRA:
3763 opcode = op_CFEBRA
3764 case ACFDBRA:
3765 opcode = op_CFDBRA
3766 case ACGEBRA:
3767 opcode = op_CGEBRA
3768 case ACGDBRA:
3769 opcode = op_CGDBRA
3770 case ACLFEBR:
3771 opcode = op_CLFEBR
3772 case ACLFDBR:
3773 opcode = op_CLFDBR
3774 case ACLGEBR:
3775 opcode = op_CLGEBR
3776 case ACLGDBR:
3777 opcode = op_CLGDBR
3778 }
3779
3780
3781 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3782
3783 case 84:
3784 l := c.regoff(&p.From)
3785 if l < 1 || l > 256 {
3786 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3787 }
3788 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3789 c.ctxt.Diag("cannot use index reg")
3790 }
3791 b1 := p.To.Reg
3792 b2 := p.GetFrom3().Reg
3793 if b1 == 0 {
3794 b1 = REGSP
3795 }
3796 if b2 == 0 {
3797 b2 = REGSP
3798 }
3799 d1 := c.regoff(&p.To)
3800 d2 := c.regoff(p.GetFrom3())
3801 if d1 < 0 || d1 >= DISP12 {
3802 if b2 == int16(regtmp(p)) {
3803 c.ctxt.Diag("regtmp(p) conflict")
3804 }
3805 if b1 != int16(regtmp(p)) {
3806 zRRE(op_LGR, regtmp(p), uint32(b1), asm)
3807 }
3808 zRIL(_a, op_AGFI, regtmp(p), uint32(d1), asm)
3809 if d1 == d2 && b1 == b2 {
3810 d2 = 0
3811 b2 = int16(regtmp(p))
3812 }
3813 d1 = 0
3814 b1 = int16(regtmp(p))
3815 }
3816 if d2 < 0 || d2 >= DISP12 {
3817 if b1 == REGTMP2 {
3818 c.ctxt.Diag("REGTMP2 conflict")
3819 }
3820 if b2 != REGTMP2 {
3821 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3822 }
3823 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3824 d2 = 0
3825 b2 = REGTMP2
3826 }
3827 var opcode uint32
3828 switch p.As {
3829 default:
3830 c.ctxt.Diag("unexpected opcode %v", p.As)
3831 case AMVC:
3832 opcode = op_MVC
3833 case AMVCIN:
3834 opcode = op_MVCIN
3835 case ACLC:
3836 opcode = op_CLC
3837
3838 b1, b2 = b2, b1
3839 d1, d2 = d2, d1
3840 case AXC:
3841 opcode = op_XC
3842 case AOC:
3843 opcode = op_OC
3844 case ANC:
3845 opcode = op_NC
3846 }
3847 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3848
3849 case 85:
3850 v := c.regoff(&p.From)
3851 if p.From.Sym == nil {
3852 if (v & 1) != 0 {
3853 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3854 }
3855 } else {
3856 c.addrilreloc(p.From.Sym, int64(v))
3857 v = 0
3858 }
3859 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3860
3861 case 86:
3862 d := c.vregoff(&p.From)
3863 x := p.From.Index
3864 b := p.From.Reg
3865 if b == 0 {
3866 b = REGSP
3867 }
3868 switch p.As {
3869 case ALA:
3870 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3871 case ALAY:
3872 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3873 }
3874
3875 case 87:
3876 v := c.vregoff(&p.From)
3877 if p.From.Sym == nil {
3878 if v&1 != 0 {
3879 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3880 }
3881 } else {
3882 c.addrilreloc(p.From.Sym, v)
3883 v = 0
3884 }
3885 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3886
3887 case 88:
3888 var opcode uint32
3889 switch p.As {
3890 case ASTCK:
3891 opcode = op_STCK
3892 case ASTCKC:
3893 opcode = op_STCKC
3894 case ASTCKE:
3895 opcode = op_STCKE
3896 case ASTCKF:
3897 opcode = op_STCKF
3898 }
3899 v := c.vregoff(&p.To)
3900 r := p.To.Reg
3901 if r == 0 {
3902 r = REGSP
3903 }
3904 zS(opcode, uint32(r), uint32(v), asm)
3905
3906 case 89:
3907 var v int32
3908 if p.To.Target() != nil {
3909 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3910 }
3911
3912
3913 r1, r2 := p.From.Reg, p.Reg
3914 if p.From.Type == obj.TYPE_CONST {
3915 r1, r2 = p.Reg, p.RestArgs[0].Reg
3916 }
3917 m3 := uint32(c.branchMask(p))
3918
3919 var opcode uint32
3920 switch p.As {
3921 case ACRJ:
3922
3923 opcode = op_CRJ
3924 case ACGRJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3925
3926 opcode = op_CGRJ
3927 case ACLRJ:
3928
3929 opcode = op_CLRJ
3930 case ACLGRJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3931
3932 opcode = op_CLGRJ
3933 }
3934
3935 if int32(int16(v)) != v {
3936
3937
3938
3939
3940
3941
3942
3943
3944 m3 ^= 0xe
3945 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(sizeRIE+sizeRIL)/2, 0, 0, m3, 0, asm)
3946 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3947 } else {
3948 zRIE(_b, opcode, uint32(r1), uint32(r2), uint32(v), 0, 0, m3, 0, asm)
3949 }
3950
3951 case 90:
3952 var v int32
3953 if p.To.Target() != nil {
3954 v = int32((p.To.Target().Pc - p.Pc) >> 1)
3955 }
3956
3957
3958 r1, i2 := p.From.Reg, p.RestArgs[0].Offset
3959 if p.From.Type == obj.TYPE_CONST {
3960 r1 = p.Reg
3961 }
3962 m3 := uint32(c.branchMask(p))
3963
3964 var opcode uint32
3965 switch p.As {
3966 case ACIJ:
3967 opcode = op_CIJ
3968 case ACGIJ, ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3969 opcode = op_CGIJ
3970 case ACLIJ:
3971 opcode = op_CLIJ
3972 case ACLGIJ, ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3973 opcode = op_CLGIJ
3974 }
3975 if int32(int16(v)) != v {
3976
3977
3978
3979
3980
3981
3982
3983
3984 m3 ^= 0xe
3985 zRIE(_c, opcode, uint32(r1), m3, uint32(sizeRIE+sizeRIL)/2, 0, 0, 0, uint32(i2), asm)
3986 zRIL(_c, op_BRCL, uint32(Always), uint32(v-sizeRIE/2), asm)
3987 } else {
3988 zRIE(_c, opcode, uint32(r1), m3, uint32(v), 0, 0, 0, uint32(i2), asm)
3989 }
3990
3991 case 91:
3992 var opcode uint32
3993 switch p.As {
3994 case ATMHH:
3995 opcode = op_TMHH
3996 case ATMHL:
3997 opcode = op_TMHL
3998 case ATMLH:
3999 opcode = op_TMLH
4000 case ATMLL:
4001 opcode = op_TMLL
4002 }
4003 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
4004
4005 case 92:
4006 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
4007
4008 case 93:
4009 v := c.vregoff(&p.To)
4010 if v != 0 {
4011 c.ctxt.Diag("invalid offset against GOT slot %v", p)
4012 }
4013 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
4014 c.cursym.AddRel(c.ctxt, obj.Reloc{
4015 Type: objabi.R_GOTPCREL,
4016 Off: int32(c.pc + 2),
4017 Siz: 4,
4018 Sym: p.From.Sym,
4019 Add: 2 + 4,
4020 })
4021
4022 case 94:
4023 zRIL(_b, op_LARL, regtmp(p), (sizeRIL+sizeRXY+sizeRI)>>1, asm)
4024 zRXY(op_LG, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4025 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
4026 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
4027 c.cursym.AddRel(c.ctxt, obj.Reloc{
4028 Type: objabi.R_TLS_LE,
4029 Off: int32(c.pc + sizeRIL + sizeRXY + sizeRI),
4030 Siz: 8,
4031 Sym: p.From.Sym,
4032 })
4033
4034 case 95:
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046 zRIL(_b, op_LARL, regtmp(p), 0, asm)
4047 c.cursym.AddRel(c.ctxt, obj.Reloc{
4048 Type: objabi.R_TLS_IE,
4049 Off: int32(c.pc + 2),
4050 Siz: 4,
4051 Sym: p.From.Sym,
4052 Add: 2 + 4,
4053 })
4054
4055
4056 zRXY(op_LGF, uint32(p.To.Reg), regtmp(p), 0, 0, asm)
4057
4058
4059
4060 case 96:
4061 length := c.vregoff(&p.From)
4062 offset := c.vregoff(&p.To)
4063 reg := p.To.Reg
4064 if reg == 0 {
4065 reg = REGSP
4066 }
4067 if length <= 0 {
4068 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
4069 }
4070 for length > 0 {
4071 if offset < 0 || offset >= DISP12 {
4072 if offset >= -DISP20/2 && offset < DISP20/2 {
4073 zRXY(op_LAY, regtmp(p), uint32(reg), 0, uint32(offset), asm)
4074 } else {
4075 if reg != int16(regtmp(p)) {
4076 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4077 }
4078 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4079 }
4080 reg = int16(regtmp(p))
4081 offset = 0
4082 }
4083 size := length
4084 if size > 256 {
4085 size = 256
4086 }
4087
4088 switch size {
4089 case 1:
4090 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
4091 case 2:
4092 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
4093 case 4:
4094 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
4095 case 8:
4096 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
4097 default:
4098 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
4099 }
4100
4101 length -= size
4102 offset += size
4103 }
4104
4105 case 97:
4106 rstart := p.From.Reg
4107 rend := p.Reg
4108 offset := c.regoff(&p.To)
4109 reg := p.To.Reg
4110 if reg == 0 {
4111 reg = REGSP
4112 }
4113 if offset < -DISP20/2 || offset >= DISP20/2 {
4114 if reg != int16(regtmp(p)) {
4115 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4116 }
4117 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4118 reg = int16(regtmp(p))
4119 offset = 0
4120 }
4121 switch p.As {
4122 case ASTMY:
4123 if offset >= 0 && offset < DISP12 {
4124 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4125 } else {
4126 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4127 }
4128 case ASTMG:
4129 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4130 }
4131
4132 case 98:
4133 rstart := p.Reg
4134 rend := p.To.Reg
4135 offset := c.regoff(&p.From)
4136 reg := p.From.Reg
4137 if reg == 0 {
4138 reg = REGSP
4139 }
4140 if offset < -DISP20/2 || offset >= DISP20/2 {
4141 if reg != int16(regtmp(p)) {
4142 zRRE(op_LGR, regtmp(p), uint32(reg), asm)
4143 }
4144 zRIL(_a, op_AGFI, regtmp(p), uint32(offset), asm)
4145 reg = int16(regtmp(p))
4146 offset = 0
4147 }
4148 switch p.As {
4149 case ALMY:
4150 if offset >= 0 && offset < DISP12 {
4151 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4152 } else {
4153 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4154 }
4155 case ALMG:
4156 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
4157 }
4158
4159 case 99:
4160 if p.To.Index != 0 {
4161 c.ctxt.Diag("cannot use indexed address")
4162 }
4163 offset := c.regoff(&p.To)
4164 if offset < -DISP20/2 || offset >= DISP20/2 {
4165 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
4166 }
4167 var opcode uint32
4168 switch p.As {
4169 case ALAA:
4170 opcode = op_LAA
4171 case ALAAG:
4172 opcode = op_LAAG
4173 case ALAAL:
4174 opcode = op_LAAL
4175 case ALAALG:
4176 opcode = op_LAALG
4177 case ALAN:
4178 opcode = op_LAN
4179 case ALANG:
4180 opcode = op_LANG
4181 case ALAX:
4182 opcode = op_LAX
4183 case ALAXG:
4184 opcode = op_LAXG
4185 case ALAO:
4186 opcode = op_LAO
4187 case ALAOG:
4188 opcode = op_LAOG
4189 }
4190 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4191
4192 case 100:
4193 op, m3, _ := vop(p.As)
4194 v1 := p.From.Reg
4195 if p.Reg != 0 {
4196 m3 = uint32(c.vregoff(&p.From))
4197 v1 = p.Reg
4198 }
4199 b2 := p.To.Reg
4200 if b2 == 0 {
4201 b2 = REGSP
4202 }
4203 d2 := uint32(c.vregoff(&p.To))
4204 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4205
4206 case 101:
4207 op, m3, _ := vop(p.As)
4208 src := &p.From
4209 if p.GetFrom3() != nil {
4210 m3 = uint32(c.vregoff(&p.From))
4211 src = p.GetFrom3()
4212 }
4213 b2 := src.Reg
4214 if b2 == 0 {
4215 b2 = REGSP
4216 }
4217 d2 := uint32(c.vregoff(src))
4218 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4219
4220 case 102:
4221 op, _, _ := vop(p.As)
4222 m3 := uint32(c.vregoff(&p.From))
4223 b2 := p.To.Reg
4224 if b2 == 0 {
4225 b2 = REGSP
4226 }
4227 d2 := uint32(c.vregoff(&p.To))
4228 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4229
4230 case 103:
4231 op, _, _ := vop(p.As)
4232 m3 := uint32(c.vregoff(&p.From))
4233 b2 := p.GetFrom3().Reg
4234 if b2 == 0 {
4235 b2 = REGSP
4236 }
4237 d2 := uint32(c.vregoff(p.GetFrom3()))
4238 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4239
4240 case 104:
4241 op, m4, _ := vop(p.As)
4242 fr := p.Reg
4243 if fr == 0 {
4244 fr = p.To.Reg
4245 }
4246 bits := uint32(c.vregoff(&p.From))
4247 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4248
4249 case 105:
4250 op, _, _ := vop(p.As)
4251 offset := uint32(c.vregoff(&p.To))
4252 reg := p.To.Reg
4253 if reg == 0 {
4254 reg = REGSP
4255 }
4256 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4257
4258 case 106:
4259 op, _, _ := vop(p.As)
4260 offset := uint32(c.vregoff(&p.From))
4261 reg := p.From.Reg
4262 if reg == 0 {
4263 reg = REGSP
4264 }
4265 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4266
4267 case 107:
4268 op, _, _ := vop(p.As)
4269 offset := uint32(c.vregoff(&p.To))
4270 reg := p.To.Reg
4271 if reg == 0 {
4272 reg = REGSP
4273 }
4274 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4275
4276 case 108:
4277 op, _, _ := vop(p.As)
4278 offset := uint32(c.vregoff(p.GetFrom3()))
4279 reg := p.GetFrom3().Reg
4280 if reg == 0 {
4281 reg = REGSP
4282 }
4283 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4284
4285 case 109:
4286 op, m3, _ := vop(p.As)
4287 i2 := uint32(c.vregoff(&p.From))
4288 if p.GetFrom3() != nil {
4289 m3 = uint32(c.vregoff(&p.From))
4290 i2 = uint32(c.vregoff(p.GetFrom3()))
4291 }
4292 switch p.As {
4293 case AVZERO:
4294 i2 = 0
4295 case AVONE:
4296 i2 = 0xffff
4297 }
4298 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4299
4300 case 110:
4301 op, m4, _ := vop(p.As)
4302 i2 := uint32(c.vregoff(&p.From))
4303 i3 := uint32(c.vregoff(p.GetFrom3()))
4304 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4305
4306 case 111:
4307 op, m4, _ := vop(p.As)
4308 i2 := uint32(c.vregoff(&p.From))
4309 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4310
4311 case 112:
4312 op, m5, _ := vop(p.As)
4313 i4 := uint32(c.vregoff(&p.From))
4314 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4315
4316 case 113:
4317 op, m4, _ := vop(p.As)
4318 m5 := singleElementMask(p.As)
4319 i3 := uint32(c.vregoff(&p.From))
4320 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4321
4322 case 114:
4323 op, m3, m5 := vop(p.As)
4324 m4 := singleElementMask(p.As)
4325 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4326
4327 case 115:
4328 op, m3, m5 := vop(p.As)
4329 m4 := singleElementMask(p.As)
4330 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4331
4332 case 117:
4333 op, m4, m5 := vop(p.As)
4334 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4335
4336 case 118:
4337 op, m4, m6 := vop(p.As)
4338 m5 := singleElementMask(p.As)
4339 v3 := p.Reg
4340 if v3 == 0 {
4341 v3 = p.To.Reg
4342 }
4343 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4344
4345 case 119:
4346 op, m4, m6 := vop(p.As)
4347 m5 := singleElementMask(p.As)
4348 v2 := p.Reg
4349 if v2 == 0 {
4350 v2 = p.To.Reg
4351 }
4352 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4353
4354 case 120:
4355 op, m6, m5 := vop(p.As)
4356 v1 := uint32(p.To.Reg)
4357 v2 := uint32(p.From.Reg)
4358 v3 := uint32(p.Reg)
4359 v4 := uint32(p.GetFrom3().Reg)
4360 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4361
4362 case 121:
4363 op, m6, _ := vop(p.As)
4364 m5 := singleElementMask(p.As)
4365 v1 := uint32(p.To.Reg)
4366 v2 := uint32(p.From.Reg)
4367 v3 := uint32(p.Reg)
4368 v4 := uint32(p.GetFrom3().Reg)
4369 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4370
4371 case 122:
4372 op, _, _ := vop(p.As)
4373 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4374
4375 case 123:
4376 op, _, _ := vop(p.As)
4377 m4 := c.regoff(&p.From)
4378 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4379
4380 case 124:
4381 var opcode uint32
4382 switch p.As {
4383 default:
4384 c.ctxt.Diag("unexpected opcode %v", p.As)
4385 case AKM, AKMC, AKLMD:
4386 if p.From.Reg == REG_R0 {
4387 c.ctxt.Diag("input must not be R0 in %v", p)
4388 }
4389 if p.From.Reg&1 != 0 {
4390 c.ctxt.Diag("input must be even register in %v", p)
4391 }
4392 if p.To.Reg == REG_R0 {
4393 c.ctxt.Diag("second argument must not be R0 in %v", p)
4394 }
4395 if p.To.Reg&1 != 0 {
4396 c.ctxt.Diag("second argument must be even register in %v", p)
4397 }
4398 if p.As == AKM {
4399 opcode = op_KM
4400 } else if p.As == AKMC {
4401 opcode = op_KMC
4402 } else {
4403 opcode = op_KLMD
4404 }
4405 case AKIMD:
4406 if p.To.Reg == REG_R0 {
4407 c.ctxt.Diag("second argument must not be R0 in %v", p)
4408 }
4409 if p.To.Reg&1 != 0 {
4410 c.ctxt.Diag("second argument must be even register in %v", p)
4411 }
4412 opcode = op_KIMD
4413 }
4414 zRRE(opcode, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4415
4416 case 125:
4417 if p.To.Reg == REG_R0 {
4418 c.ctxt.Diag("second argument must not be R0 in %v", p)
4419 }
4420 if p.To.Reg&1 != 0 {
4421 c.ctxt.Diag("second argument must be an even register in %v", p)
4422 }
4423 zRRE(op_KDSA, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4424
4425 case 126:
4426 var opcode uint32
4427 switch p.As {
4428 default:
4429 c.ctxt.Diag("unexpected opcode %v", p.As)
4430 case AKMA, AKMCTR:
4431 if p.From.Reg == REG_R0 {
4432 c.ctxt.Diag("input argument must not be R0 in %v", p)
4433 }
4434 if p.From.Reg&1 != 0 {
4435 c.ctxt.Diag("input argument must be even register in %v", p)
4436 }
4437 if p.To.Reg == REG_R0 {
4438 c.ctxt.Diag("output argument must not be R0 in %v", p)
4439 }
4440 if p.To.Reg&1 != 0 {
4441 c.ctxt.Diag("output argument must be an even register in %v", p)
4442 }
4443 if p.Reg == REG_R0 {
4444 c.ctxt.Diag("third argument must not be R0 in %v", p)
4445 }
4446 if p.Reg&1 != 0 {
4447 c.ctxt.Diag("third argument must be even register in %v", p)
4448 }
4449 if p.As == AKMA {
4450 opcode = op_KMA
4451 } else if p.As == AKMCTR {
4452 opcode = op_KMCTR
4453 }
4454 }
4455 zRRF(opcode, uint32(p.Reg), 0, uint32(p.From.Reg), uint32(p.To.Reg), asm)
4456 }
4457 }
4458
4459 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4460 c.instoffset = 0
4461 if a != nil {
4462 c.aclass(a)
4463 }
4464 return c.instoffset
4465 }
4466
4467 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4468 return int32(c.vregoff(a))
4469 }
4470
4471
4472 func isU12(displacement int32) bool {
4473 return displacement >= 0 && displacement < DISP12
4474 }
4475
4476
4477 func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
4478 switch a {
4479 case AFMOVD:
4480 return op_LD, true
4481 case AFMOVS:
4482 return op_LE, true
4483 }
4484 return 0, false
4485 }
4486
4487
4488 func (c *ctxtz) zopload(a obj.As) uint32 {
4489 switch a {
4490
4491 case AMOVD:
4492 return op_LG
4493 case AMOVW:
4494 return op_LGF
4495 case AMOVWZ:
4496 return op_LLGF
4497 case AMOVH:
4498 return op_LGH
4499 case AMOVHZ:
4500 return op_LLGH
4501 case AMOVB:
4502 return op_LGB
4503 case AMOVBZ:
4504 return op_LLGC
4505
4506
4507 case AFMOVD:
4508 return op_LDY
4509 case AFMOVS:
4510 return op_LEY
4511
4512
4513 case AMOVDBR:
4514 return op_LRVG
4515 case AMOVWBR:
4516 return op_LRV
4517 case AMOVHBR:
4518 return op_LRVH
4519 }
4520
4521 c.ctxt.Diag("unknown store opcode %v", a)
4522 return 0
4523 }
4524
4525
4526 func (c *ctxtz) zopstore12(a obj.As) (uint32, bool) {
4527 switch a {
4528 case AFMOVD:
4529 return op_STD, true
4530 case AFMOVS:
4531 return op_STE, true
4532 case AMOVW, AMOVWZ:
4533 return op_ST, true
4534 case AMOVH, AMOVHZ:
4535 return op_STH, true
4536 case AMOVB, AMOVBZ:
4537 return op_STC, true
4538 }
4539 return 0, false
4540 }
4541
4542
4543 func (c *ctxtz) zopstore(a obj.As) uint32 {
4544 switch a {
4545
4546 case AMOVD:
4547 return op_STG
4548 case AMOVW, AMOVWZ:
4549 return op_STY
4550 case AMOVH, AMOVHZ:
4551 return op_STHY
4552 case AMOVB, AMOVBZ:
4553 return op_STCY
4554
4555
4556 case AFMOVD:
4557 return op_STDY
4558 case AFMOVS:
4559 return op_STEY
4560
4561
4562 case AMOVDBR:
4563 return op_STRVG
4564 case AMOVWBR:
4565 return op_STRV
4566 case AMOVHBR:
4567 return op_STRVH
4568 }
4569
4570 c.ctxt.Diag("unknown store opcode %v", a)
4571 return 0
4572 }
4573
4574
4575 func (c *ctxtz) zoprre(a obj.As) uint32 {
4576 switch a {
4577 case ACMP:
4578 return op_CGR
4579 case ACMPU:
4580 return op_CLGR
4581 case AFCMPO:
4582 return op_KDBR
4583 case AFCMPU:
4584 return op_CDBR
4585 case ACEBR:
4586 return op_CEBR
4587 }
4588 c.ctxt.Diag("unknown rre opcode %v", a)
4589 return 0
4590 }
4591
4592
4593 func (c *ctxtz) zoprr(a obj.As) uint32 {
4594 switch a {
4595 case ACMPW:
4596 return op_CR
4597 case ACMPWU:
4598 return op_CLR
4599 }
4600 c.ctxt.Diag("unknown rr opcode %v", a)
4601 return 0
4602 }
4603
4604
4605 func (c *ctxtz) zopril(a obj.As) uint32 {
4606 switch a {
4607 case ACMP:
4608 return op_CGFI
4609 case ACMPU:
4610 return op_CLGFI
4611 case ACMPW:
4612 return op_CFI
4613 case ACMPWU:
4614 return op_CLFI
4615 }
4616 c.ctxt.Diag("unknown ril opcode %v", a)
4617 return 0
4618 }
4619
4620
4621 const (
4622 sizeE = 2
4623 sizeI = 2
4624 sizeIE = 4
4625 sizeMII = 6
4626 sizeRI = 4
4627 sizeRI1 = 4
4628 sizeRI2 = 4
4629 sizeRI3 = 4
4630 sizeRIE = 6
4631 sizeRIE1 = 6
4632 sizeRIE2 = 6
4633 sizeRIE3 = 6
4634 sizeRIE4 = 6
4635 sizeRIE5 = 6
4636 sizeRIE6 = 6
4637 sizeRIL = 6
4638 sizeRIL1 = 6
4639 sizeRIL2 = 6
4640 sizeRIL3 = 6
4641 sizeRIS = 6
4642 sizeRR = 2
4643 sizeRRD = 4
4644 sizeRRE = 4
4645 sizeRRF = 4
4646 sizeRRF1 = 4
4647 sizeRRF2 = 4
4648 sizeRRF3 = 4
4649 sizeRRF4 = 4
4650 sizeRRF5 = 4
4651 sizeRRR = 2
4652 sizeRRS = 6
4653 sizeRS = 4
4654 sizeRS1 = 4
4655 sizeRS2 = 4
4656 sizeRSI = 4
4657 sizeRSL = 6
4658 sizeRSY = 6
4659 sizeRSY1 = 6
4660 sizeRSY2 = 6
4661 sizeRX = 4
4662 sizeRX1 = 4
4663 sizeRX2 = 4
4664 sizeRXE = 6
4665 sizeRXF = 6
4666 sizeRXY = 6
4667 sizeRXY1 = 6
4668 sizeRXY2 = 6
4669 sizeS = 4
4670 sizeSI = 4
4671 sizeSIL = 6
4672 sizeSIY = 6
4673 sizeSMI = 6
4674 sizeSS = 6
4675 sizeSS1 = 6
4676 sizeSS2 = 6
4677 sizeSS3 = 6
4678 sizeSS4 = 6
4679 sizeSS5 = 6
4680 sizeSS6 = 6
4681 sizeSSE = 6
4682 sizeSSF = 6
4683 )
4684
4685
4686 type form int
4687
4688 const (
4689 _a form = iota
4690 _b
4691 _c
4692 _d
4693 _e
4694 _f
4695 )
4696
4697 func zE(op uint32, asm *[]byte) {
4698 *asm = append(*asm, uint8(op>>8), uint8(op))
4699 }
4700
4701 func zI(op, i1 uint32, asm *[]byte) {
4702 *asm = append(*asm, uint8(op>>8), uint8(i1))
4703 }
4704
4705 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4706 *asm = append(*asm,
4707 uint8(op>>8),
4708 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4709 uint8(ri2),
4710 uint8(ri3>>16),
4711 uint8(ri3>>8),
4712 uint8(ri3))
4713 }
4714
4715 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4716 *asm = append(*asm,
4717 uint8(op>>8),
4718 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4719 uint8(i2_ri2>>8),
4720 uint8(i2_ri2))
4721 }
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4735 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4736
4737 switch f {
4738 default:
4739 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4740 case _f:
4741 *asm = append(*asm, uint8(i3), uint8(i4))
4742 }
4743
4744 switch f {
4745 case _a, _b:
4746 *asm = append(*asm, uint8(m3)<<4)
4747 default:
4748 *asm = append(*asm, uint8(i2_i5))
4749 }
4750
4751 *asm = append(*asm, uint8(op))
4752 }
4753
4754 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4755 if f == _a || f == _b {
4756 r1_m1 = r1_m1 - obj.RBaseS390X
4757 }
4758 *asm = append(*asm,
4759 uint8(op>>8),
4760 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4761 uint8(i2_ri2>>24),
4762 uint8(i2_ri2>>16),
4763 uint8(i2_ri2>>8),
4764 uint8(i2_ri2))
4765 }
4766
4767 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4768 *asm = append(*asm,
4769 uint8(op>>8),
4770 (uint8(r1)<<4)|uint8(m3&0x0F),
4771 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4772 uint8(d4),
4773 uint8(i2),
4774 uint8(op))
4775 }
4776
4777 func zRR(op, r1, r2 uint32, asm *[]byte) {
4778 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4779 }
4780
4781 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4782 *asm = append(*asm,
4783 uint8(op>>8),
4784 uint8(op),
4785 uint8(r1)<<4,
4786 (uint8(r3)<<4)|uint8(r2&0x0F))
4787 }
4788
4789 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4790 *asm = append(*asm,
4791 uint8(op>>8),
4792 uint8(op),
4793 0,
4794 (uint8(r1)<<4)|uint8(r2&0x0F))
4795 }
4796
4797 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4798 *asm = append(*asm,
4799 uint8(op>>8),
4800 uint8(op),
4801 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4802 (uint8(r1)<<4)|uint8(r2&0x0F))
4803 }
4804
4805 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4806 *asm = append(*asm,
4807 uint8(op>>8),
4808 (uint8(r1)<<4)|uint8(r2&0x0F),
4809 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4810 uint8(d4),
4811 uint8(m3)<<4,
4812 uint8(op))
4813 }
4814
4815 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4816 *asm = append(*asm,
4817 uint8(op>>8),
4818 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4819 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4820 uint8(d2))
4821 }
4822
4823 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4824 *asm = append(*asm,
4825 uint8(op>>8),
4826 (uint8(r1)<<4)|uint8(r3&0x0F),
4827 uint8(ri2>>8),
4828 uint8(ri2))
4829 }
4830
4831 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4832 *asm = append(*asm,
4833 uint8(op>>8),
4834 uint8(l1),
4835 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4836 uint8(d2),
4837 uint8(op))
4838 }
4839
4840 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4841 dl2 := uint16(d2) & 0x0FFF
4842 *asm = append(*asm,
4843 uint8(op>>8),
4844 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4845 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4846 uint8(dl2),
4847 uint8(d2>>12),
4848 uint8(op))
4849 }
4850
4851 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4852 *asm = append(*asm,
4853 uint8(op>>8),
4854 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4855 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4856 uint8(d2))
4857 }
4858
4859 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4860 *asm = append(*asm,
4861 uint8(op>>8),
4862 (uint8(r1)<<4)|uint8(x2&0x0F),
4863 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4864 uint8(d2),
4865 uint8(m3)<<4,
4866 uint8(op))
4867 }
4868
4869 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4870 *asm = append(*asm,
4871 uint8(op>>8),
4872 (uint8(r3)<<4)|uint8(x2&0x0F),
4873 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4874 uint8(d2),
4875 uint8(m1)<<4,
4876 uint8(op))
4877 }
4878
4879 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4880 dl2 := uint16(d2) & 0x0FFF
4881 *asm = append(*asm,
4882 uint8(op>>8),
4883 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4884 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4885 uint8(dl2),
4886 uint8(d2>>12),
4887 uint8(op))
4888 }
4889
4890 func zS(op, b2, d2 uint32, asm *[]byte) {
4891 *asm = append(*asm,
4892 uint8(op>>8),
4893 uint8(op),
4894 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4895 uint8(d2))
4896 }
4897
4898 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4899 *asm = append(*asm,
4900 uint8(op>>8),
4901 uint8(i2),
4902 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4903 uint8(d1))
4904 }
4905
4906 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4907 *asm = append(*asm,
4908 uint8(op>>8),
4909 uint8(op),
4910 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4911 uint8(d1),
4912 uint8(i2>>8),
4913 uint8(i2))
4914 }
4915
4916 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4917 dl1 := uint16(d1) & 0x0FFF
4918 *asm = append(*asm,
4919 uint8(op>>8),
4920 uint8(i2),
4921 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4922 uint8(dl1),
4923 uint8(d1>>12),
4924 uint8(op))
4925 }
4926
4927 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4928 *asm = append(*asm,
4929 uint8(op>>8),
4930 uint8(m1)<<4,
4931 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4932 uint8(d3),
4933 uint8(ri2>>8),
4934 uint8(ri2))
4935 }
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4948 *asm = append(*asm, uint8(op>>8))
4949
4950 switch f {
4951 case _a:
4952 *asm = append(*asm, uint8(l1_r1))
4953 case _b, _c, _d, _e:
4954 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4955 case _f:
4956 *asm = append(*asm, uint8(l2_i3_r3))
4957 }
4958
4959 *asm = append(*asm,
4960 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4961 uint8(d1_d2),
4962 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4963 uint8(d2_d4))
4964 }
4965
4966 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4967 *asm = append(*asm,
4968 uint8(op>>8),
4969 uint8(op),
4970 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4971 uint8(d1),
4972 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4973 uint8(d2))
4974 }
4975
4976 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4977 *asm = append(*asm,
4978 uint8(op>>8),
4979 (uint8(r3)<<4)|(uint8(op)&0x0F),
4980 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4981 uint8(d1),
4982 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4983 uint8(d2))
4984 }
4985
4986 func rxb(va, vb, vc, vd uint32) uint8 {
4987 mask := uint8(0)
4988 if va >= REG_V16 && va <= REG_V31 {
4989 mask |= 0x8
4990 }
4991 if vb >= REG_V16 && vb <= REG_V31 {
4992 mask |= 0x4
4993 }
4994 if vc >= REG_V16 && vc <= REG_V31 {
4995 mask |= 0x2
4996 }
4997 if vd >= REG_V16 && vd <= REG_V31 {
4998 mask |= 0x1
4999 }
5000 return mask
5001 }
5002
5003 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
5004 *asm = append(*asm,
5005 uint8(op>>8),
5006 (uint8(v1)<<4)|(uint8(x2)&0xf),
5007 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5008 uint8(d2),
5009 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5010 uint8(op))
5011 }
5012
5013 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
5014 *asm = append(*asm,
5015 uint8(op>>8),
5016 (uint8(v1)<<4)|(uint8(v2)&0xf),
5017 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5018 uint8(d2),
5019 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5020 uint8(op))
5021 }
5022
5023 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
5024 *asm = append(*asm,
5025 uint8(op>>8),
5026 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
5027 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
5028 uint8(d2),
5029 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
5030 uint8(op))
5031 }
5032
5033 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
5034 *asm = append(*asm,
5035 uint8(op>>8),
5036 (uint8(v1)<<4)|(uint8(v2)&0xf),
5037 0,
5038 (uint8(m5)<<4)|(uint8(m4)&0xf),
5039 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
5040 uint8(op))
5041 }
5042
5043 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
5044 *asm = append(*asm,
5045 uint8(op>>8),
5046 (uint8(v1)<<4)|(uint8(v2)&0xf),
5047 uint8(v3)<<4,
5048 uint8(m5)<<4,
5049 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5050 uint8(op))
5051 }
5052
5053 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
5054 *asm = append(*asm,
5055 uint8(op>>8),
5056 (uint8(v1)<<4)|(uint8(v2)&0xf),
5057 uint8(v3)<<4,
5058 (uint8(m6)<<4)|(uint8(m5)&0xf),
5059 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
5060 uint8(op))
5061 }
5062
5063 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
5064 *asm = append(*asm,
5065 uint8(op>>8),
5066 (uint8(v1)<<4)|(uint8(v2)&0xf),
5067 (uint8(v3)<<4)|(uint8(m5)&0xf),
5068 uint8(m6)<<4,
5069 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5070 uint8(op))
5071 }
5072
5073 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
5074 *asm = append(*asm,
5075 uint8(op>>8),
5076 (uint8(v1)<<4)|(uint8(v2)&0xf),
5077 (uint8(v3)<<4)|(uint8(m6)&0xf),
5078 uint8(m5),
5079 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
5080 uint8(op))
5081 }
5082
5083 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
5084 *asm = append(*asm,
5085 uint8(op>>8),
5086 (uint8(v1)<<4)|(uint8(r2)&0xf),
5087 uint8(r3)<<4,
5088 0,
5089 rxb(v1, 0, 0, 0),
5090 uint8(op))
5091 }
5092
5093 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
5094 *asm = append(*asm,
5095 uint8(op>>8),
5096 uint8(v1)<<4,
5097 uint8(i2>>8),
5098 uint8(i2),
5099 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
5100 uint8(op))
5101 }
5102
5103 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
5104 *asm = append(*asm,
5105 uint8(op>>8),
5106 uint8(v1)<<4,
5107 uint8(i2),
5108 uint8(i3),
5109 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
5110 uint8(op))
5111 }
5112
5113 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
5114 *asm = append(*asm,
5115 uint8(op>>8),
5116 (uint8(v1)<<4)|(uint8(v3)&0xf),
5117 uint8(i2>>8),
5118 uint8(i2),
5119 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
5120 uint8(op))
5121 }
5122
5123 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
5124 *asm = append(*asm,
5125 uint8(op>>8),
5126 (uint8(v1)<<4)|(uint8(v2)&0xf),
5127 uint8(v3)<<4,
5128 uint8(i4),
5129 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
5130 uint8(op))
5131 }
5132
5133 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
5134 *asm = append(*asm,
5135 uint8(op>>8),
5136 (uint8(v1)<<4)|(uint8(v2)&0xf),
5137 uint8(i3>>4),
5138 (uint8(i3)<<4)|(uint8(m5)&0xf),
5139 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
5140 uint8(op))
5141 }
5142
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