Source file src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go

Documentation: cmd/vendor/golang.org/x/arch/arm64/arm64asm

     1  // Copyright 2017 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package arm64asm
     6  
     7  import (
     8  	"encoding/binary"
     9  	"fmt"
    10  )
    11  
    12  type instArgs [5]instArg
    13  
    14  // An instFormat describes the format of an instruction encoding.
    15  // An instruction with 32-bit value x matches the format if x&mask == value
    16  // and the predicator: canDecode(x) return true.
    17  type instFormat struct {
    18  	mask  uint32
    19  	value uint32
    20  	op    Op
    21  	// args describe how to decode the instruction arguments.
    22  	// args is stored as a fixed-size array.
    23  	// if there are fewer than len(args) arguments, args[i] == 0 marks
    24  	// the end of the argument list.
    25  	args      instArgs
    26  	canDecode func(instr uint32) bool
    27  }
    28  
    29  var (
    30  	errShort   = fmt.Errorf("truncated instruction")
    31  	errUnknown = fmt.Errorf("unknown instruction")
    32  )
    33  
    34  var decoderCover []bool
    35  
    36  func init() {
    37  	decoderCover = make([]bool, len(instFormats))
    38  }
    39  
    40  // Decode decodes the 4 bytes in src as a single instruction.
    41  func Decode(src []byte) (inst Inst, err error) {
    42  	if len(src) < 4 {
    43  		return Inst{}, errShort
    44  	}
    45  
    46  	x := binary.LittleEndian.Uint32(src)
    47  
    48  Search:
    49  	for i := range instFormats {
    50  		f := &instFormats[i]
    51  		if x&f.mask != f.value {
    52  			continue
    53  		}
    54  		if f.canDecode != nil && !f.canDecode(x) {
    55  			continue
    56  		}
    57  		// Decode args.
    58  		var args Args
    59  		for j, aop := range f.args {
    60  			if aop == 0 {
    61  				break
    62  			}
    63  			arg := decodeArg(aop, x)
    64  			if arg == nil { // Cannot decode argument
    65  				continue Search
    66  			}
    67  			args[j] = arg
    68  		}
    69  		decoderCover[i] = true
    70  		inst = Inst{
    71  			Op:   f.op,
    72  			Args: args,
    73  			Enc:  x,
    74  		}
    75  		return inst, nil
    76  	}
    77  	return Inst{}, errUnknown
    78  }
    79  
    80  // decodeArg decodes the arg described by aop from the instruction bits x.
    81  // It returns nil if x cannot be decoded according to aop.
    82  func decodeArg(aop instArg, x uint32) Arg {
    83  	switch aop {
    84  	default:
    85  		return nil
    86  
    87  	case arg_Da:
    88  		return D0 + Reg((x>>10)&(1<<5-1))
    89  
    90  	case arg_Dd:
    91  		return D0 + Reg(x&(1<<5-1))
    92  
    93  	case arg_Dm:
    94  		return D0 + Reg((x>>16)&(1<<5-1))
    95  
    96  	case arg_Dn:
    97  		return D0 + Reg((x>>5)&(1<<5-1))
    98  
    99  	case arg_Hd:
   100  		return H0 + Reg(x&(1<<5-1))
   101  
   102  	case arg_Hn:
   103  		return H0 + Reg((x>>5)&(1<<5-1))
   104  
   105  	case arg_IAddSub:
   106  		imm12 := (x >> 10) & (1<<12 - 1)
   107  		shift := (x >> 22) & (1<<2 - 1)
   108  		if shift > 1 {
   109  			return nil
   110  		}
   111  		shift = shift * 12
   112  		return ImmShift{uint16(imm12), uint8(shift)}
   113  
   114  	case arg_Sa:
   115  		return S0 + Reg((x>>10)&(1<<5-1))
   116  
   117  	case arg_Sd:
   118  		return S0 + Reg(x&(1<<5-1))
   119  
   120  	case arg_Sm:
   121  		return S0 + Reg((x>>16)&(1<<5-1))
   122  
   123  	case arg_Sn:
   124  		return S0 + Reg((x>>5)&(1<<5-1))
   125  
   126  	case arg_Wa:
   127  		return W0 + Reg((x>>10)&(1<<5-1))
   128  
   129  	case arg_Wd:
   130  		return W0 + Reg(x&(1<<5-1))
   131  
   132  	case arg_Wds:
   133  		return RegSP(W0) + RegSP(x&(1<<5-1))
   134  
   135  	case arg_Wm:
   136  		return W0 + Reg((x>>16)&(1<<5-1))
   137  
   138  	case arg_Rm_extend__UXTB_0__UXTH_1__UXTW_2__LSL_UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
   139  		return handle_ExtendedRegister(x, true)
   140  
   141  	case arg_Wm_extend__UXTB_0__UXTH_1__LSL_UXTW_2__UXTX_3__SXTB_4__SXTH_5__SXTW_6__SXTX_7__0_4:
   142  		return handle_ExtendedRegister(x, false)
   143  
   144  	case arg_Wn:
   145  		return W0 + Reg((x>>5)&(1<<5-1))
   146  
   147  	case arg_Wns:
   148  		return RegSP(W0) + RegSP((x>>5)&(1<<5-1))
   149  
   150  	case arg_Xa:
   151  		return X0 + Reg((x>>10)&(1<<5-1))
   152  
   153  	case arg_Xd:
   154  		return X0 + Reg(x&(1<<5-1))
   155  
   156  	case arg_Xds:
   157  		return RegSP(X0) + RegSP(x&(1<<5-1))
   158  
   159  	case arg_Xm:
   160  		return X0 + Reg((x>>16)&(1<<5-1))
   161  
   162  	case arg_Wm_shift__LSL_0__LSR_1__ASR_2__0_31:
   163  		return handle_ImmediateShiftedRegister(x, 31, true, false)
   164  
   165  	case arg_Wm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_31:
   166  		return handle_ImmediateShiftedRegister(x, 31, true, true)
   167  
   168  	case arg_Xm_shift__LSL_0__LSR_1__ASR_2__0_63:
   169  		return handle_ImmediateShiftedRegister(x, 63, false, false)
   170  
   171  	case arg_Xm_shift__LSL_0__LSR_1__ASR_2__ROR_3__0_63:
   172  		return handle_ImmediateShiftedRegister(x, 63, false, true)
   173  
   174  	case arg_Xn:
   175  		return X0 + Reg((x>>5)&(1<<5-1))
   176  
   177  	case arg_Xns:
   178  		return RegSP(X0) + RegSP((x>>5)&(1<<5-1))
   179  
   180  	case arg_slabel_imm14_2:
   181  		imm14 := ((x >> 5) & (1<<14 - 1))
   182  		return PCRel(((int64(imm14) << 2) << 48) >> 48)
   183  
   184  	case arg_slabel_imm19_2:
   185  		imm19 := ((x >> 5) & (1<<19 - 1))
   186  		return PCRel(((int64(imm19) << 2) << 43) >> 43)
   187  
   188  	case arg_slabel_imm26_2:
   189  		imm26 := (x & (1<<26 - 1))
   190  		return PCRel(((int64(imm26) << 2) << 36) >> 36)
   191  
   192  	case arg_slabel_immhi_immlo_0:
   193  		immhi := ((x >> 5) & (1<<19 - 1))
   194  		immlo := ((x >> 29) & (1<<2 - 1))
   195  		immhilo := (immhi)<<2 | immlo
   196  		return PCRel((int64(immhilo) << 43) >> 43)
   197  
   198  	case arg_slabel_immhi_immlo_12:
   199  		immhi := ((x >> 5) & (1<<19 - 1))
   200  		immlo := ((x >> 29) & (1<<2 - 1))
   201  		immhilo := (immhi)<<2 | immlo
   202  		return PCRel(((int64(immhilo) << 12) << 31) >> 31)
   203  
   204  	case arg_Xns_mem:
   205  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   206  		return MemImmediate{Rn, AddrOffset, 0}
   207  
   208  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__1_1:
   209  		return handle_MemExtend(x, 1, false)
   210  
   211  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__2_1:
   212  		return handle_MemExtend(x, 2, false)
   213  
   214  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__3_1:
   215  		return handle_MemExtend(x, 3, false)
   216  
   217  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__absent_0__0_1:
   218  		return handle_MemExtend(x, 1, true)
   219  
   220  	case arg_Xns_mem_optional_imm12_1_unsigned:
   221  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   222  		imm12 := (x >> 10) & (1<<12 - 1)
   223  		return MemImmediate{Rn, AddrOffset, int32(imm12)}
   224  
   225  	case arg_Xns_mem_optional_imm12_2_unsigned:
   226  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   227  		imm12 := (x >> 10) & (1<<12 - 1)
   228  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 1)}
   229  
   230  	case arg_Xns_mem_optional_imm12_4_unsigned:
   231  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   232  		imm12 := (x >> 10) & (1<<12 - 1)
   233  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 2)}
   234  
   235  	case arg_Xns_mem_optional_imm12_8_unsigned:
   236  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   237  		imm12 := (x >> 10) & (1<<12 - 1)
   238  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 3)}
   239  
   240  	case arg_Xns_mem_optional_imm7_4_signed:
   241  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   242  		imm7 := (x >> 15) & (1<<7 - 1)
   243  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 2)) << 23) >> 23}
   244  
   245  	case arg_Xns_mem_optional_imm7_8_signed:
   246  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   247  		imm7 := (x >> 15) & (1<<7 - 1)
   248  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 3)) << 22) >> 22}
   249  
   250  	case arg_Xns_mem_optional_imm9_1_signed:
   251  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   252  		imm9 := (x >> 12) & (1<<9 - 1)
   253  		return MemImmediate{Rn, AddrOffset, (int32(imm9) << 23) >> 23}
   254  
   255  	case arg_Xns_mem_post_imm7_4_signed:
   256  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   257  		imm7 := (x >> 15) & (1<<7 - 1)
   258  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 2)) << 23) >> 23}
   259  
   260  	case arg_Xns_mem_post_imm7_8_signed:
   261  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   262  		imm7 := (x >> 15) & (1<<7 - 1)
   263  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 3)) << 22) >> 22}
   264  
   265  	case arg_Xns_mem_post_imm9_1_signed:
   266  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   267  		imm9 := (x >> 12) & (1<<9 - 1)
   268  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm9)) << 23) >> 23}
   269  
   270  	case arg_Xns_mem_wb_imm7_4_signed:
   271  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   272  		imm7 := (x >> 15) & (1<<7 - 1)
   273  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 2)) << 23) >> 23}
   274  
   275  	case arg_Xns_mem_wb_imm7_8_signed:
   276  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   277  		imm7 := (x >> 15) & (1<<7 - 1)
   278  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 3)) << 22) >> 22}
   279  
   280  	case arg_Xns_mem_wb_imm9_1_signed:
   281  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
   282  		imm9 := (x >> 12) & (1<<9 - 1)
   283  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm9)) << 23) >> 23}
   284  
   285  	case arg_Ws:
   286  		return W0 + Reg((x>>16)&(1<<5-1))
   287  
   288  	case arg_Wt:
   289  		return W0 + Reg(x&(1<<5-1))
   290  
   291  	case arg_Wt2:
   292  		return W0 + Reg((x>>10)&(1<<5-1))
   293  
   294  	case arg_Xs:
   295  		return X0 + Reg((x>>16)&(1<<5-1))
   296  
   297  	case arg_Xt:
   298  		return X0 + Reg(x&(1<<5-1))
   299  
   300  	case arg_Xt2:
   301  		return X0 + Reg((x>>10)&(1<<5-1))
   302  
   303  	case arg_immediate_0_127_CRm_op2:
   304  		crm_op2 := (x >> 5) & (1<<7 - 1)
   305  		return Imm_hint(crm_op2)
   306  
   307  	case arg_immediate_0_15_CRm:
   308  		crm := (x >> 8) & (1<<4 - 1)
   309  		return Imm{crm, false}
   310  
   311  	case arg_immediate_0_15_nzcv:
   312  		nzcv := x & (1<<4 - 1)
   313  		return Imm{nzcv, false}
   314  
   315  	case arg_immediate_0_31_imm5:
   316  		imm5 := (x >> 16) & (1<<5 - 1)
   317  		return Imm{imm5, false}
   318  
   319  	case arg_immediate_0_31_immr:
   320  		immr := (x >> 16) & (1<<6 - 1)
   321  		if immr > 31 {
   322  			return nil
   323  		}
   324  		return Imm{immr, false}
   325  
   326  	case arg_immediate_0_31_imms:
   327  		imms := (x >> 10) & (1<<6 - 1)
   328  		if imms > 31 {
   329  			return nil
   330  		}
   331  		return Imm{imms, true}
   332  
   333  	case arg_immediate_0_63_b5_b40:
   334  		b5 := (x >> 31) & 1
   335  		b40 := (x >> 19) & (1<<5 - 1)
   336  		return Imm{(b5 << 5) | b40, true}
   337  
   338  	case arg_immediate_0_63_immr:
   339  		immr := (x >> 16) & (1<<6 - 1)
   340  		return Imm{immr, false}
   341  
   342  	case arg_immediate_0_63_imms:
   343  		imms := (x >> 10) & (1<<6 - 1)
   344  		return Imm{imms, true}
   345  
   346  	case arg_immediate_0_65535_imm16:
   347  		imm16 := (x >> 5) & (1<<16 - 1)
   348  		return Imm{imm16, false}
   349  
   350  	case arg_immediate_0_7_op1:
   351  		op1 := (x >> 16) & (1<<3 - 1)
   352  		return Imm{op1, true}
   353  
   354  	case arg_immediate_0_7_op2:
   355  		op2 := (x >> 5) & (1<<3 - 1)
   356  		return Imm{op2, true}
   357  
   358  	case arg_immediate_ASR_SBFM_32M_bitfield_0_31_immr:
   359  		immr := (x >> 16) & (1<<6 - 1)
   360  		if immr > 31 {
   361  			return nil
   362  		}
   363  		return Imm{immr, true}
   364  
   365  	case arg_immediate_ASR_SBFM_64M_bitfield_0_63_immr:
   366  		immr := (x >> 16) & (1<<6 - 1)
   367  		return Imm{immr, true}
   368  
   369  	case arg_immediate_BFI_BFM_32M_bitfield_lsb_32_immr:
   370  		immr := (x >> 16) & (1<<6 - 1)
   371  		if immr > 31 {
   372  			return nil
   373  		}
   374  		return Imm{32 - immr, true}
   375  
   376  	case arg_immediate_BFI_BFM_32M_bitfield_width_32_imms:
   377  		imms := (x >> 10) & (1<<6 - 1)
   378  		if imms > 31 {
   379  			return nil
   380  		}
   381  		return Imm{imms + 1, true}
   382  
   383  	case arg_immediate_BFI_BFM_64M_bitfield_lsb_64_immr:
   384  		immr := (x >> 16) & (1<<6 - 1)
   385  		return Imm{64 - immr, true}
   386  
   387  	case arg_immediate_BFI_BFM_64M_bitfield_width_64_imms:
   388  		imms := (x >> 10) & (1<<6 - 1)
   389  		return Imm{imms + 1, true}
   390  
   391  	case arg_immediate_BFXIL_BFM_32M_bitfield_lsb_32_immr:
   392  		immr := (x >> 16) & (1<<6 - 1)
   393  		if immr > 31 {
   394  			return nil
   395  		}
   396  		return Imm{immr, true}
   397  
   398  	case arg_immediate_BFXIL_BFM_32M_bitfield_width_32_imms:
   399  		immr := (x >> 16) & (1<<6 - 1)
   400  		imms := (x >> 10) & (1<<6 - 1)
   401  		width := imms - immr + 1
   402  		if width < 1 || width > 32-immr {
   403  			return nil
   404  		}
   405  		return Imm{width, true}
   406  
   407  	case arg_immediate_BFXIL_BFM_64M_bitfield_lsb_64_immr:
   408  		immr := (x >> 16) & (1<<6 - 1)
   409  		return Imm{immr, true}
   410  
   411  	case arg_immediate_BFXIL_BFM_64M_bitfield_width_64_imms:
   412  		immr := (x >> 16) & (1<<6 - 1)
   413  		imms := (x >> 10) & (1<<6 - 1)
   414  		width := imms - immr + 1
   415  		if width < 1 || width > 64-immr {
   416  			return nil
   417  		}
   418  		return Imm{width, true}
   419  
   420  	case arg_immediate_bitmask_32_imms_immr:
   421  		return handle_bitmasks(x, 32)
   422  
   423  	case arg_immediate_bitmask_64_N_imms_immr:
   424  		return handle_bitmasks(x, 64)
   425  
   426  	case arg_immediate_LSL_UBFM_32M_bitfield_0_31_immr:
   427  		imms := (x >> 10) & (1<<6 - 1)
   428  		shift := 31 - imms
   429  		if shift > 31 {
   430  			return nil
   431  		}
   432  		return Imm{shift, true}
   433  
   434  	case arg_immediate_LSL_UBFM_64M_bitfield_0_63_immr:
   435  		imms := (x >> 10) & (1<<6 - 1)
   436  		shift := 63 - imms
   437  		if shift > 63 {
   438  			return nil
   439  		}
   440  		return Imm{shift, true}
   441  
   442  	case arg_immediate_LSR_UBFM_32M_bitfield_0_31_immr:
   443  		immr := (x >> 16) & (1<<6 - 1)
   444  		if immr > 31 {
   445  			return nil
   446  		}
   447  		return Imm{immr, true}
   448  
   449  	case arg_immediate_LSR_UBFM_64M_bitfield_0_63_immr:
   450  		immr := (x >> 16) & (1<<6 - 1)
   451  		return Imm{immr, true}
   452  
   453  	case arg_immediate_optional_0_15_CRm:
   454  		crm := (x >> 8) & (1<<4 - 1)
   455  		return Imm_clrex(crm)
   456  
   457  	case arg_immediate_optional_0_65535_imm16:
   458  		imm16 := (x >> 5) & (1<<16 - 1)
   459  		return Imm_dcps(imm16)
   460  
   461  	case arg_immediate_OptLSL_amount_16_0_16:
   462  		imm16 := (x >> 5) & (1<<16 - 1)
   463  		hw := (x >> 21) & (1<<2 - 1)
   464  		shift := hw * 16
   465  		if shift > 16 {
   466  			return nil
   467  		}
   468  		return ImmShift{uint16(imm16), uint8(shift)}
   469  
   470  	case arg_immediate_OptLSL_amount_16_0_48:
   471  		imm16 := (x >> 5) & (1<<16 - 1)
   472  		hw := (x >> 21) & (1<<2 - 1)
   473  		shift := hw * 16
   474  		return ImmShift{uint16(imm16), uint8(shift)}
   475  
   476  	case arg_immediate_SBFIZ_SBFM_32M_bitfield_lsb_32_immr:
   477  		immr := (x >> 16) & (1<<6 - 1)
   478  		if immr > 31 {
   479  			return nil
   480  		}
   481  		return Imm{32 - immr, true}
   482  
   483  	case arg_immediate_SBFIZ_SBFM_32M_bitfield_width_32_imms:
   484  		imms := (x >> 10) & (1<<6 - 1)
   485  		if imms > 31 {
   486  			return nil
   487  		}
   488  		return Imm{imms + 1, true}
   489  
   490  	case arg_immediate_SBFIZ_SBFM_64M_bitfield_lsb_64_immr:
   491  		immr := (x >> 16) & (1<<6 - 1)
   492  		return Imm{64 - immr, true}
   493  
   494  	case arg_immediate_SBFIZ_SBFM_64M_bitfield_width_64_imms:
   495  		imms := (x >> 10) & (1<<6 - 1)
   496  		return Imm{imms + 1, true}
   497  
   498  	case arg_immediate_SBFX_SBFM_32M_bitfield_lsb_32_immr:
   499  		immr := (x >> 16) & (1<<6 - 1)
   500  		if immr > 31 {
   501  			return nil
   502  		}
   503  		return Imm{immr, true}
   504  
   505  	case arg_immediate_SBFX_SBFM_32M_bitfield_width_32_imms:
   506  		immr := (x >> 16) & (1<<6 - 1)
   507  		imms := (x >> 10) & (1<<6 - 1)
   508  		width := imms - immr + 1
   509  		if width < 1 || width > 32-immr {
   510  			return nil
   511  		}
   512  		return Imm{width, true}
   513  
   514  	case arg_immediate_SBFX_SBFM_64M_bitfield_lsb_64_immr:
   515  		immr := (x >> 16) & (1<<6 - 1)
   516  		return Imm{immr, true}
   517  
   518  	case arg_immediate_SBFX_SBFM_64M_bitfield_width_64_imms:
   519  		immr := (x >> 16) & (1<<6 - 1)
   520  		imms := (x >> 10) & (1<<6 - 1)
   521  		width := imms - immr + 1
   522  		if width < 1 || width > 64-immr {
   523  			return nil
   524  		}
   525  		return Imm{width, true}
   526  
   527  	case arg_immediate_shift_32_implicit_imm16_hw:
   528  		imm16 := (x >> 5) & (1<<16 - 1)
   529  		hw := (x >> 21) & (1<<2 - 1)
   530  		shift := hw * 16
   531  		if shift > 16 {
   532  			return nil
   533  		}
   534  		result := uint32(imm16) << shift
   535  		return Imm{result, false}
   536  
   537  	case arg_immediate_shift_32_implicit_inverse_imm16_hw:
   538  		imm16 := (x >> 5) & (1<<16 - 1)
   539  		hw := (x >> 21) & (1<<2 - 1)
   540  		shift := hw * 16
   541  		if shift > 16 {
   542  			return nil
   543  		}
   544  		result := uint32(imm16) << shift
   545  		return Imm{^result, false}
   546  
   547  	case arg_immediate_shift_64_implicit_imm16_hw:
   548  		imm16 := (x >> 5) & (1<<16 - 1)
   549  		hw := (x >> 21) & (1<<2 - 1)
   550  		shift := hw * 16
   551  		result := uint64(imm16) << shift
   552  		return Imm64{result, false}
   553  
   554  	case arg_immediate_shift_64_implicit_inverse_imm16_hw:
   555  		imm16 := (x >> 5) & (1<<16 - 1)
   556  		hw := (x >> 21) & (1<<2 - 1)
   557  		shift := hw * 16
   558  		result := uint64(imm16) << shift
   559  		return Imm64{^result, false}
   560  
   561  	case arg_immediate_UBFIZ_UBFM_32M_bitfield_lsb_32_immr:
   562  		immr := (x >> 16) & (1<<6 - 1)
   563  		if immr > 31 {
   564  			return nil
   565  		}
   566  		return Imm{32 - immr, true}
   567  
   568  	case arg_immediate_UBFIZ_UBFM_32M_bitfield_width_32_imms:
   569  		imms := (x >> 10) & (1<<6 - 1)
   570  		if imms > 31 {
   571  			return nil
   572  		}
   573  		return Imm{imms + 1, true}
   574  
   575  	case arg_immediate_UBFIZ_UBFM_64M_bitfield_lsb_64_immr:
   576  		immr := (x >> 16) & (1<<6 - 1)
   577  		return Imm{64 - immr, true}
   578  
   579  	case arg_immediate_UBFIZ_UBFM_64M_bitfield_width_64_imms:
   580  		imms := (x >> 10) & (1<<6 - 1)
   581  		return Imm{imms + 1, true}
   582  
   583  	case arg_immediate_UBFX_UBFM_32M_bitfield_lsb_32_immr:
   584  		immr := (x >> 16) & (1<<6 - 1)
   585  		if immr > 31 {
   586  			return nil
   587  		}
   588  		return Imm{immr, true}
   589  
   590  	case arg_immediate_UBFX_UBFM_32M_bitfield_width_32_imms:
   591  		immr := (x >> 16) & (1<<6 - 1)
   592  		imms := (x >> 10) & (1<<6 - 1)
   593  		width := imms - immr + 1
   594  		if width < 1 || width > 32-immr {
   595  			return nil
   596  		}
   597  		return Imm{width, true}
   598  
   599  	case arg_immediate_UBFX_UBFM_64M_bitfield_lsb_64_immr:
   600  		immr := (x >> 16) & (1<<6 - 1)
   601  		return Imm{immr, true}
   602  
   603  	case arg_immediate_UBFX_UBFM_64M_bitfield_width_64_imms:
   604  		immr := (x >> 16) & (1<<6 - 1)
   605  		imms := (x >> 10) & (1<<6 - 1)
   606  		width := imms - immr + 1
   607  		if width < 1 || width > 64-immr {
   608  			return nil
   609  		}
   610  		return Imm{width, true}
   611  
   612  	case arg_Rt_31_1__W_0__X_1:
   613  		b5 := (x >> 31) & 1
   614  		Rt := x & (1<<5 - 1)
   615  		if b5 == 0 {
   616  			return W0 + Reg(Rt)
   617  		} else {
   618  			return X0 + Reg(Rt)
   619  		}
   620  
   621  	case arg_cond_AllowALNV_Normal:
   622  		cond := (x >> 12) & (1<<4 - 1)
   623  		return Cond{uint8(cond), false}
   624  
   625  	case arg_conditional:
   626  		cond := x & (1<<4 - 1)
   627  		return Cond{uint8(cond), false}
   628  
   629  	case arg_cond_NotAllowALNV_Invert:
   630  		cond := (x >> 12) & (1<<4 - 1)
   631  		if (cond >> 1) == 7 {
   632  			return nil
   633  		}
   634  		return Cond{uint8(cond), true}
   635  
   636  	case arg_Cm:
   637  		CRm := (x >> 8) & (1<<4 - 1)
   638  		return Imm_c(CRm)
   639  
   640  	case arg_Cn:
   641  		CRn := (x >> 12) & (1<<4 - 1)
   642  		return Imm_c(CRn)
   643  
   644  	case arg_option_DMB_BO_system_CRm:
   645  		CRm := (x >> 8) & (1<<4 - 1)
   646  		return Imm_option(CRm)
   647  
   648  	case arg_option_DSB_BO_system_CRm:
   649  		CRm := (x >> 8) & (1<<4 - 1)
   650  		return Imm_option(CRm)
   651  
   652  	case arg_option_ISB_BI_system_CRm:
   653  		CRm := (x >> 8) & (1<<4 - 1)
   654  		if CRm == 15 {
   655  			return Imm_option(CRm)
   656  		}
   657  		return Imm{CRm, false}
   658  
   659  	case arg_prfop_Rt:
   660  		Rt := x & (1<<5 - 1)
   661  		return Imm_prfop(Rt)
   662  
   663  	case arg_pstatefield_op1_op2__SPSel_05__DAIFSet_36__DAIFClr_37:
   664  		op1 := (x >> 16) & (1<<3 - 1)
   665  		op2 := (x >> 5) & (1<<3 - 1)
   666  		if (op1 == 0) && (op2 == 5) {
   667  			return SPSel
   668  		} else if (op1 == 3) && (op2 == 6) {
   669  			return DAIFSet
   670  		} else if (op1 == 3) && (op2 == 7) {
   671  			return DAIFClr
   672  		}
   673  		return nil
   674  
   675  	case arg_sysreg_o0_op1_CRn_CRm_op2:
   676  		op0 := (x >> 19) & (1<<2 - 1)
   677  		op1 := (x >> 16) & (1<<3 - 1)
   678  		CRn := (x >> 12) & (1<<4 - 1)
   679  		CRm := (x >> 8) & (1<<4 - 1)
   680  		op2 := (x >> 5) & (1<<3 - 1)
   681  		return Systemreg{uint8(op0), uint8(op1), uint8(CRn), uint8(CRm), uint8(op2)}
   682  
   683  	case arg_sysop_AT_SYS_CR_system:
   684  		//TODO: system instruction
   685  		return nil
   686  
   687  	case arg_sysop_SYS_CR_system:
   688  		//TODO: system instruction
   689  		return nil
   690  
   691  	case arg_sysop_DC_SYS_CR_system, arg_sysop_TLBI_SYS_CR_system:
   692  		op1 := (x >> 16) & 7
   693  		cn := (x >> 12) & 15
   694  		cm := (x >> 8) & 15
   695  		op2 := (x >> 5) & 7
   696  		sysInst := sysInstFields{uint8(op1), uint8(cn), uint8(cm), uint8(op2)}
   697  		attrs := sysInst.getAttrs()
   698  		reg := int(x & 31)
   699  		if !attrs.hasOperand2 {
   700  			if reg == 31 {
   701  				return sysOp{sysInst, 0, false}
   702  			}
   703  			// This instruction is undefined if the Rt field is not set to 31.
   704  			return nil
   705  		}
   706  		return sysOp{sysInst, X0 + Reg(reg), true}
   707  
   708  	case arg_Bt:
   709  		return B0 + Reg(x&(1<<5-1))
   710  
   711  	case arg_Dt:
   712  		return D0 + Reg(x&(1<<5-1))
   713  
   714  	case arg_Dt2:
   715  		return D0 + Reg((x>>10)&(1<<5-1))
   716  
   717  	case arg_Ht:
   718  		return H0 + Reg(x&(1<<5-1))
   719  
   720  	case arg_immediate_0_63_immh_immb__UIntimmhimmb64_8:
   721  		immh := (x >> 19) & (1<<4 - 1)
   722  		if (immh & 8) == 0 {
   723  			return nil
   724  		}
   725  		immb := (x >> 16) & (1<<3 - 1)
   726  		return Imm{(immh << 3) + immb - 64, true}
   727  
   728  	case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4:
   729  		immh := (x >> 19) & (1<<4 - 1)
   730  		immb := (x >> 16) & (1<<3 - 1)
   731  		if immh == 1 {
   732  			return Imm{(immh << 3) + immb - 8, true}
   733  		} else if (immh >> 1) == 1 {
   734  			return Imm{(immh << 3) + immb - 16, true}
   735  		} else if (immh >> 2) == 1 {
   736  			return Imm{(immh << 3) + immb - 32, true}
   737  		} else {
   738  			return nil
   739  		}
   740  
   741  	case arg_immediate_0_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
   742  		fallthrough
   743  
   744  	case arg_immediate_0_width_m1_immh_immb__UIntimmhimmb8_1__UIntimmhimmb16_2__UIntimmhimmb32_4__UIntimmhimmb64_8:
   745  		immh := (x >> 19) & (1<<4 - 1)
   746  		immb := (x >> 16) & (1<<3 - 1)
   747  		if immh == 1 {
   748  			return Imm{(immh << 3) + immb - 8, true}
   749  		} else if (immh >> 1) == 1 {
   750  			return Imm{(immh << 3) + immb - 16, true}
   751  		} else if (immh >> 2) == 1 {
   752  			return Imm{(immh << 3) + immb - 32, true}
   753  		} else if (immh >> 3) == 1 {
   754  			return Imm{(immh << 3) + immb - 64, true}
   755  		} else {
   756  			return nil
   757  		}
   758  
   759  	case arg_immediate_0_width_size__8_0__16_1__32_2:
   760  		size := (x >> 22) & (1<<2 - 1)
   761  		switch size {
   762  		case 0:
   763  			return Imm{8, true}
   764  		case 1:
   765  			return Imm{16, true}
   766  		case 2:
   767  			return Imm{32, true}
   768  		default:
   769  			return nil
   770  		}
   771  
   772  	case arg_immediate_1_64_immh_immb__128UIntimmhimmb_8:
   773  		immh := (x >> 19) & (1<<4 - 1)
   774  		if (immh & 8) == 0 {
   775  			return nil
   776  		}
   777  		immb := (x >> 16) & (1<<3 - 1)
   778  		return Imm{128 - ((immh << 3) + immb), true}
   779  
   780  	case arg_immediate_1_width_immh_immb__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
   781  		fallthrough
   782  
   783  	case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4:
   784  		immh := (x >> 19) & (1<<4 - 1)
   785  		immb := (x >> 16) & (1<<3 - 1)
   786  		if immh == 1 {
   787  			return Imm{16 - ((immh << 3) + immb), true}
   788  		} else if (immh >> 1) == 1 {
   789  			return Imm{32 - ((immh << 3) + immb), true}
   790  		} else if (immh >> 2) == 1 {
   791  			return Imm{64 - ((immh << 3) + immb), true}
   792  		} else {
   793  			return nil
   794  		}
   795  
   796  	case arg_immediate_1_width_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__16UIntimmhimmb_1__32UIntimmhimmb_2__64UIntimmhimmb_4__128UIntimmhimmb_8:
   797  		immh := (x >> 19) & (1<<4 - 1)
   798  		immb := (x >> 16) & (1<<3 - 1)
   799  		if immh == 1 {
   800  			return Imm{16 - ((immh << 3) + immb), true}
   801  		} else if (immh >> 1) == 1 {
   802  			return Imm{32 - ((immh << 3) + immb), true}
   803  		} else if (immh >> 2) == 1 {
   804  			return Imm{64 - ((immh << 3) + immb), true}
   805  		} else if (immh >> 3) == 1 {
   806  			return Imm{128 - ((immh << 3) + immb), true}
   807  		} else {
   808  			return nil
   809  		}
   810  
   811  	case arg_immediate_8x8_a_b_c_d_e_f_g_h:
   812  		var imm uint64
   813  		if x&(1<<5) != 0 {
   814  			imm = (1 << 8) - 1
   815  		} else {
   816  			imm = 0
   817  		}
   818  		if x&(1<<6) != 0 {
   819  			imm += ((1 << 8) - 1) << 8
   820  		}
   821  		if x&(1<<7) != 0 {
   822  			imm += ((1 << 8) - 1) << 16
   823  		}
   824  		if x&(1<<8) != 0 {
   825  			imm += ((1 << 8) - 1) << 24
   826  		}
   827  		if x&(1<<9) != 0 {
   828  			imm += ((1 << 8) - 1) << 32
   829  		}
   830  		if x&(1<<16) != 0 {
   831  			imm += ((1 << 8) - 1) << 40
   832  		}
   833  		if x&(1<<17) != 0 {
   834  			imm += ((1 << 8) - 1) << 48
   835  		}
   836  		if x&(1<<18) != 0 {
   837  			imm += ((1 << 8) - 1) << 56
   838  		}
   839  		return Imm64{imm, false}
   840  
   841  	case arg_immediate_exp_3_pre_4_a_b_c_d_e_f_g_h:
   842  		pre := (x >> 5) & (1<<4 - 1)
   843  		exp := 1 - ((x >> 17) & 1)
   844  		exp = (exp << 2) + (((x >> 16) & 1) << 1) + ((x >> 9) & 1)
   845  		s := ((x >> 18) & 1)
   846  		return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
   847  
   848  	case arg_immediate_exp_3_pre_4_imm8:
   849  		pre := (x >> 13) & (1<<4 - 1)
   850  		exp := 1 - ((x >> 19) & 1)
   851  		exp = (exp << 2) + ((x >> 17) & (1<<2 - 1))
   852  		s := ((x >> 20) & 1)
   853  		return Imm_fp{uint8(s), int8(exp) - 3, uint8(pre)}
   854  
   855  	case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__64UIntimmhimmb_4__128UIntimmhimmb_8:
   856  		fallthrough
   857  
   858  	case arg_immediate_fbits_min_1_max_0_sub_0_immh_immb__SEEAdvancedSIMDmodifiedimmediate_0__64UIntimmhimmb_4__128UIntimmhimmb_8:
   859  		immh := (x >> 19) & (1<<4 - 1)
   860  		immb := (x >> 16) & (1<<3 - 1)
   861  		if (immh >> 2) == 1 {
   862  			return Imm{64 - ((immh << 3) + immb), true}
   863  		} else if (immh >> 3) == 1 {
   864  			return Imm{128 - ((immh << 3) + immb), true}
   865  		} else {
   866  			return nil
   867  		}
   868  
   869  	case arg_immediate_fbits_min_1_max_32_sub_64_scale:
   870  		scale := (x >> 10) & (1<<6 - 1)
   871  		fbits := 64 - scale
   872  		if fbits > 32 {
   873  			return nil
   874  		}
   875  		return Imm{fbits, true}
   876  
   877  	case arg_immediate_fbits_min_1_max_64_sub_64_scale:
   878  		scale := (x >> 10) & (1<<6 - 1)
   879  		fbits := 64 - scale
   880  		return Imm{fbits, true}
   881  
   882  	case arg_immediate_floatzero:
   883  		return Imm{0, true}
   884  
   885  	case arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
   886  		Q := (x >> 30) & 1
   887  		imm4 := (x >> 11) & (1<<4 - 1)
   888  		if Q == 1 || (imm4>>3) == 0 {
   889  			return Imm{imm4, true}
   890  		} else {
   891  			return nil
   892  		}
   893  
   894  	case arg_immediate_MSL__a_b_c_d_e_f_g_h_cmode__8_0__16_1:
   895  		var shift uint8
   896  		imm8 := (x >> 16) & (1<<3 - 1)
   897  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   898  		if (x>>12)&1 == 0 {
   899  			shift = 8 + 128
   900  		} else {
   901  			shift = 16 + 128
   902  		}
   903  		return ImmShift{uint16(imm8), shift}
   904  
   905  	case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1:
   906  		imm8 := (x >> 16) & (1<<3 - 1)
   907  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   908  		cmode1 := (x >> 13) & 1
   909  		shift := 8 * cmode1
   910  		return ImmShift{uint16(imm8), uint8(shift)}
   911  
   912  	case arg_immediate_OptLSL__a_b_c_d_e_f_g_h_cmode__0_0__8_1__16_2__24_3:
   913  		imm8 := (x >> 16) & (1<<3 - 1)
   914  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   915  		cmode1 := (x >> 13) & (1<<2 - 1)
   916  		shift := 8 * cmode1
   917  		return ImmShift{uint16(imm8), uint8(shift)}
   918  
   919  	case arg_immediate_OptLSLZero__a_b_c_d_e_f_g_h:
   920  		imm8 := (x >> 16) & (1<<3 - 1)
   921  		imm8 = (imm8 << 5) | ((x >> 5) & (1<<5 - 1))
   922  		return ImmShift{uint16(imm8), 0}
   923  
   924  	case arg_immediate_zero:
   925  		return Imm{0, true}
   926  
   927  	case arg_Qd:
   928  		return Q0 + Reg(x&(1<<5-1))
   929  
   930  	case arg_Qn:
   931  		return Q0 + Reg((x>>5)&(1<<5-1))
   932  
   933  	case arg_Qt:
   934  		return Q0 + Reg(x&(1<<5-1))
   935  
   936  	case arg_Qt2:
   937  		return Q0 + Reg((x>>10)&(1<<5-1))
   938  
   939  	case arg_Rn_16_5__W_1__W_2__W_4__X_8:
   940  		imm5 := (x >> 16) & (1<<5 - 1)
   941  		if ((imm5 & 1) == 1) || ((imm5 & 2) == 2) || ((imm5 & 4) == 4) {
   942  			return W0 + Reg((x>>5)&(1<<5-1))
   943  		} else if (imm5 & 8) == 8 {
   944  			return X0 + Reg((x>>5)&(1<<5-1))
   945  		} else {
   946  			return nil
   947  		}
   948  
   949  	case arg_St:
   950  		return S0 + Reg(x&(1<<5-1))
   951  
   952  	case arg_St2:
   953  		return S0 + Reg((x>>10)&(1<<5-1))
   954  
   955  	case arg_Vd_16_5__B_1__H_2__S_4__D_8:
   956  		imm5 := (x >> 16) & (1<<5 - 1)
   957  		Rd := x & (1<<5 - 1)
   958  		if imm5&1 == 1 {
   959  			return B0 + Reg(Rd)
   960  		} else if imm5&2 == 2 {
   961  			return H0 + Reg(Rd)
   962  		} else if imm5&4 == 4 {
   963  			return S0 + Reg(Rd)
   964  		} else if imm5&8 == 8 {
   965  			return D0 + Reg(Rd)
   966  		} else {
   967  			return nil
   968  		}
   969  
   970  	case arg_Vd_19_4__B_1__H_2__S_4:
   971  		immh := (x >> 19) & (1<<4 - 1)
   972  		Rd := x & (1<<5 - 1)
   973  		if immh == 1 {
   974  			return B0 + Reg(Rd)
   975  		} else if immh>>1 == 1 {
   976  			return H0 + Reg(Rd)
   977  		} else if immh>>2 == 1 {
   978  			return S0 + Reg(Rd)
   979  		} else {
   980  			return nil
   981  		}
   982  
   983  	case arg_Vd_19_4__B_1__H_2__S_4__D_8:
   984  		immh := (x >> 19) & (1<<4 - 1)
   985  		Rd := x & (1<<5 - 1)
   986  		if immh == 1 {
   987  			return B0 + Reg(Rd)
   988  		} else if immh>>1 == 1 {
   989  			return H0 + Reg(Rd)
   990  		} else if immh>>2 == 1 {
   991  			return S0 + Reg(Rd)
   992  		} else if immh>>3 == 1 {
   993  			return D0 + Reg(Rd)
   994  		} else {
   995  			return nil
   996  		}
   997  
   998  	case arg_Vd_19_4__D_8:
   999  		immh := (x >> 19) & (1<<4 - 1)
  1000  		Rd := x & (1<<5 - 1)
  1001  		if immh>>3 == 1 {
  1002  			return D0 + Reg(Rd)
  1003  		} else {
  1004  			return nil
  1005  		}
  1006  
  1007  	case arg_Vd_19_4__S_4__D_8:
  1008  		immh := (x >> 19) & (1<<4 - 1)
  1009  		Rd := x & (1<<5 - 1)
  1010  		if immh>>2 == 1 {
  1011  			return S0 + Reg(Rd)
  1012  		} else if immh>>3 == 1 {
  1013  			return D0 + Reg(Rd)
  1014  		} else {
  1015  			return nil
  1016  		}
  1017  
  1018  	case arg_Vd_22_1__S_0:
  1019  		sz := (x >> 22) & 1
  1020  		Rd := x & (1<<5 - 1)
  1021  		if sz == 0 {
  1022  			return S0 + Reg(Rd)
  1023  		} else {
  1024  			return nil
  1025  		}
  1026  
  1027  	case arg_Vd_22_1__S_0__D_1:
  1028  		sz := (x >> 22) & 1
  1029  		Rd := x & (1<<5 - 1)
  1030  		if sz == 0 {
  1031  			return S0 + Reg(Rd)
  1032  		} else {
  1033  			return D0 + Reg(Rd)
  1034  		}
  1035  
  1036  	case arg_Vd_22_1__S_1:
  1037  		sz := (x >> 22) & 1
  1038  		Rd := x & (1<<5 - 1)
  1039  		if sz == 1 {
  1040  			return S0 + Reg(Rd)
  1041  		} else {
  1042  			return nil
  1043  		}
  1044  
  1045  	case arg_Vd_22_2__B_0__H_1__S_2:
  1046  		size := (x >> 22) & (1<<2 - 1)
  1047  		Rd := x & (1<<5 - 1)
  1048  		if size == 0 {
  1049  			return B0 + Reg(Rd)
  1050  		} else if size == 1 {
  1051  			return H0 + Reg(Rd)
  1052  		} else if size == 2 {
  1053  			return S0 + Reg(Rd)
  1054  		} else {
  1055  			return nil
  1056  		}
  1057  
  1058  	case arg_Vd_22_2__B_0__H_1__S_2__D_3:
  1059  		size := (x >> 22) & (1<<2 - 1)
  1060  		Rd := x & (1<<5 - 1)
  1061  		if size == 0 {
  1062  			return B0 + Reg(Rd)
  1063  		} else if size == 1 {
  1064  			return H0 + Reg(Rd)
  1065  		} else if size == 2 {
  1066  			return S0 + Reg(Rd)
  1067  		} else {
  1068  			return D0 + Reg(Rd)
  1069  		}
  1070  
  1071  	case arg_Vd_22_2__D_3:
  1072  		size := (x >> 22) & (1<<2 - 1)
  1073  		Rd := x & (1<<5 - 1)
  1074  		if size == 3 {
  1075  			return D0 + Reg(Rd)
  1076  		} else {
  1077  			return nil
  1078  		}
  1079  
  1080  	case arg_Vd_22_2__H_0__S_1__D_2:
  1081  		size := (x >> 22) & (1<<2 - 1)
  1082  		Rd := x & (1<<5 - 1)
  1083  		if size == 0 {
  1084  			return H0 + Reg(Rd)
  1085  		} else if size == 1 {
  1086  			return S0 + Reg(Rd)
  1087  		} else if size == 2 {
  1088  			return D0 + Reg(Rd)
  1089  		} else {
  1090  			return nil
  1091  		}
  1092  
  1093  	case arg_Vd_22_2__H_1__S_2:
  1094  		size := (x >> 22) & (1<<2 - 1)
  1095  		Rd := x & (1<<5 - 1)
  1096  		if size == 1 {
  1097  			return H0 + Reg(Rd)
  1098  		} else if size == 2 {
  1099  			return S0 + Reg(Rd)
  1100  		} else {
  1101  			return nil
  1102  		}
  1103  
  1104  	case arg_Vd_22_2__S_1__D_2:
  1105  		size := (x >> 22) & (1<<2 - 1)
  1106  		Rd := x & (1<<5 - 1)
  1107  		if size == 1 {
  1108  			return S0 + Reg(Rd)
  1109  		} else if size == 2 {
  1110  			return D0 + Reg(Rd)
  1111  		} else {
  1112  			return nil
  1113  		}
  1114  
  1115  	case arg_Vd_arrangement_16B:
  1116  		Rd := x & (1<<5 - 1)
  1117  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1118  
  1119  	case arg_Vd_arrangement_2D:
  1120  		Rd := x & (1<<5 - 1)
  1121  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1122  
  1123  	case arg_Vd_arrangement_4S:
  1124  		Rd := x & (1<<5 - 1)
  1125  		return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1126  
  1127  	case arg_Vd_arrangement_D_index__1:
  1128  		Rd := x & (1<<5 - 1)
  1129  		return RegisterWithArrangementAndIndex{V0 + Reg(Rd), ArrangementD, 1, 0}
  1130  
  1131  	case arg_Vd_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
  1132  		var a Arrangement
  1133  		var index uint32
  1134  		Rd := x & (1<<5 - 1)
  1135  		imm5 := (x >> 16) & (1<<5 - 1)
  1136  		if imm5&1 == 1 {
  1137  			a = ArrangementB
  1138  			index = imm5 >> 1
  1139  		} else if imm5&2 == 2 {
  1140  			a = ArrangementH
  1141  			index = imm5 >> 2
  1142  		} else if imm5&4 == 4 {
  1143  			a = ArrangementS
  1144  			index = imm5 >> 3
  1145  		} else if imm5&8 == 8 {
  1146  			a = ArrangementD
  1147  			index = imm5 >> 4
  1148  		} else {
  1149  			return nil
  1150  		}
  1151  		return RegisterWithArrangementAndIndex{V0 + Reg(Rd), a, uint8(index), 0}
  1152  
  1153  	case arg_Vd_arrangement_imm5_Q___8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1154  		Rd := x & (1<<5 - 1)
  1155  		imm5 := (x >> 16) & (1<<5 - 1)
  1156  		Q := (x >> 30) & 1
  1157  		if imm5&1 == 1 {
  1158  			if Q == 0 {
  1159  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1160  			} else {
  1161  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1162  			}
  1163  		} else if imm5&2 == 2 {
  1164  			if Q == 0 {
  1165  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1166  			} else {
  1167  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1168  			}
  1169  		} else if imm5&4 == 4 {
  1170  			if Q == 0 {
  1171  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1172  			} else {
  1173  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1174  			}
  1175  		} else if (imm5&8 == 8) && (Q == 1) {
  1176  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1177  		} else {
  1178  			return nil
  1179  		}
  1180  
  1181  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
  1182  		Rd := x & (1<<5 - 1)
  1183  		immh := (x >> 19) & (1<<4 - 1)
  1184  		Q := (x >> 30) & 1
  1185  		if immh>>2 == 1 {
  1186  			if Q == 0 {
  1187  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1188  			} else {
  1189  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1190  			}
  1191  		} else if immh>>3 == 1 {
  1192  			if Q == 1 {
  1193  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1194  			}
  1195  		}
  1196  		return nil
  1197  
  1198  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
  1199  		Rd := x & (1<<5 - 1)
  1200  		immh := (x >> 19) & (1<<4 - 1)
  1201  		Q := (x >> 30) & 1
  1202  		if immh == 1 {
  1203  			if Q == 0 {
  1204  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1205  			} else {
  1206  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1207  			}
  1208  		} else if immh>>1 == 1 {
  1209  			if Q == 0 {
  1210  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1211  			} else {
  1212  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1213  			}
  1214  		} else if immh>>2 == 1 {
  1215  			if Q == 0 {
  1216  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1217  			} else {
  1218  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1219  			}
  1220  		}
  1221  		return nil
  1222  
  1223  	case arg_Vd_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1224  		Rd := x & (1<<5 - 1)
  1225  		immh := (x >> 19) & (1<<4 - 1)
  1226  		Q := (x >> 30) & 1
  1227  		if immh == 1 {
  1228  			if Q == 0 {
  1229  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1230  			} else {
  1231  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1232  			}
  1233  		} else if immh>>1 == 1 {
  1234  			if Q == 0 {
  1235  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1236  			} else {
  1237  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1238  			}
  1239  		} else if immh>>2 == 1 {
  1240  			if Q == 0 {
  1241  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1242  			} else {
  1243  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1244  			}
  1245  		} else if immh>>3 == 1 {
  1246  			if Q == 1 {
  1247  				return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1248  			}
  1249  		}
  1250  		return nil
  1251  
  1252  	case arg_Vd_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
  1253  		Rd := x & (1<<5 - 1)
  1254  		immh := (x >> 19) & (1<<4 - 1)
  1255  		if immh == 1 {
  1256  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1257  		} else if immh>>1 == 1 {
  1258  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1259  		} else if immh>>2 == 1 {
  1260  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1261  		}
  1262  		return nil
  1263  
  1264  	case arg_Vd_arrangement_Q___2S_0__4S_1:
  1265  		Rd := x & (1<<5 - 1)
  1266  		Q := (x >> 30) & 1
  1267  		if Q == 0 {
  1268  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1269  		} else {
  1270  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1271  		}
  1272  
  1273  	case arg_Vd_arrangement_Q___4H_0__8H_1:
  1274  		Rd := x & (1<<5 - 1)
  1275  		Q := (x >> 30) & 1
  1276  		if Q == 0 {
  1277  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1278  		} else {
  1279  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1280  		}
  1281  
  1282  	case arg_Vd_arrangement_Q___8B_0__16B_1:
  1283  		Rd := x & (1<<5 - 1)
  1284  		Q := (x >> 30) & 1
  1285  		if Q == 0 {
  1286  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1287  		} else {
  1288  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1289  		}
  1290  
  1291  	case arg_Vd_arrangement_Q_sz___2S_00__4S_10__2D_11:
  1292  		Rd := x & (1<<5 - 1)
  1293  		Q := (x >> 30) & 1
  1294  		sz := (x >> 22) & 1
  1295  		if sz == 0 && Q == 0 {
  1296  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1297  		} else if sz == 0 && Q == 1 {
  1298  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1299  		} else if sz == 1 && Q == 1 {
  1300  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1301  		}
  1302  		return nil
  1303  
  1304  	case arg_Vd_arrangement_size___4S_1__2D_2:
  1305  		Rd := x & (1<<5 - 1)
  1306  		size := (x >> 22) & 3
  1307  		if size == 1 {
  1308  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1309  		} else if size == 2 {
  1310  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1311  		}
  1312  		return nil
  1313  
  1314  	case arg_Vd_arrangement_size___8H_0__1Q_3:
  1315  		Rd := x & (1<<5 - 1)
  1316  		size := (x >> 22) & 3
  1317  		if size == 0 {
  1318  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1319  		} else if size == 3 {
  1320  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1Q, 0}
  1321  		}
  1322  		return nil
  1323  
  1324  	case arg_Vd_arrangement_size___8H_0__4S_1__2D_2:
  1325  		Rd := x & (1<<5 - 1)
  1326  		size := (x >> 22) & 3
  1327  		if size == 0 {
  1328  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1329  		} else if size == 1 {
  1330  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1331  		} else if size == 2 {
  1332  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1333  		}
  1334  		return nil
  1335  
  1336  	case arg_Vd_arrangement_size_Q___4H_00__8H_01__2S_10__4S_11__1D_20__2D_21:
  1337  		Rd := x & (1<<5 - 1)
  1338  		size := (x >> 22) & 3
  1339  		Q := (x >> 30) & 1
  1340  		if size == 0 && Q == 0 {
  1341  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1342  		} else if size == 0 && Q == 1 {
  1343  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1344  		} else if size == 1 && Q == 0 {
  1345  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1346  		} else if size == 1 && Q == 1 {
  1347  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1348  		} else if size == 2 && Q == 0 {
  1349  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement1D, 0}
  1350  		} else if size == 2 && Q == 1 {
  1351  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1352  		}
  1353  		return nil
  1354  
  1355  	case arg_Vd_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  1356  		Rd := x & (1<<5 - 1)
  1357  		size := (x >> 22) & 3
  1358  		Q := (x >> 30) & 1
  1359  		if size == 1 && Q == 0 {
  1360  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1361  		} else if size == 1 && Q == 1 {
  1362  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1363  		} else if size == 2 && Q == 0 {
  1364  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1365  		} else if size == 2 && Q == 1 {
  1366  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1367  		}
  1368  		return nil
  1369  
  1370  	case arg_Vd_arrangement_size_Q___8B_00__16B_01:
  1371  		Rd := x & (1<<5 - 1)
  1372  		size := (x >> 22) & 3
  1373  		Q := (x >> 30) & 1
  1374  		if size == 0 && Q == 0 {
  1375  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1376  		} else if size == 0 && Q == 1 {
  1377  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1378  		}
  1379  		return nil
  1380  
  1381  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
  1382  		Rd := x & (1<<5 - 1)
  1383  		size := (x >> 22) & 3
  1384  		Q := (x >> 30) & 1
  1385  		if size == 0 && Q == 0 {
  1386  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1387  		} else if size == 0 && Q == 1 {
  1388  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1389  		} else if size == 1 && Q == 0 {
  1390  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1391  		} else if size == 1 && Q == 1 {
  1392  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1393  		}
  1394  		return nil
  1395  
  1396  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  1397  		Rd := x & (1<<5 - 1)
  1398  		size := (x >> 22) & 3
  1399  		Q := (x >> 30) & 1
  1400  		if size == 0 && Q == 0 {
  1401  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1402  		} else if size == 0 && Q == 1 {
  1403  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1404  		} else if size == 1 && Q == 0 {
  1405  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1406  		} else if size == 1 && Q == 1 {
  1407  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1408  		} else if size == 2 && Q == 0 {
  1409  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1410  		} else if size == 2 && Q == 1 {
  1411  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1412  		}
  1413  		return nil
  1414  
  1415  	case arg_Vd_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  1416  		Rd := x & (1<<5 - 1)
  1417  		size := (x >> 22) & 3
  1418  		Q := (x >> 30) & 1
  1419  		if size == 0 && Q == 0 {
  1420  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8B, 0}
  1421  		} else if size == 0 && Q == 1 {
  1422  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement16B, 0}
  1423  		} else if size == 1 && Q == 0 {
  1424  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1425  		} else if size == 1 && Q == 1 {
  1426  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1427  		} else if size == 2 && Q == 0 {
  1428  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1429  		} else if size == 2 && Q == 1 {
  1430  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1431  		} else if size == 3 && Q == 1 {
  1432  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1433  		}
  1434  		return nil
  1435  
  1436  	case arg_Vd_arrangement_sz___4S_0__2D_1:
  1437  		Rd := x & (1<<5 - 1)
  1438  		sz := (x >> 22) & 1
  1439  		if sz == 0 {
  1440  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1441  		} else {
  1442  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1443  		}
  1444  
  1445  	case arg_Vd_arrangement_sz_Q___2S_00__4S_01:
  1446  		Rd := x & (1<<5 - 1)
  1447  		sz := (x >> 22) & 1
  1448  		Q := (x >> 30) & 1
  1449  		if sz == 0 && Q == 0 {
  1450  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1451  		} else if sz == 0 && Q == 1 {
  1452  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1453  		}
  1454  		return nil
  1455  
  1456  	case arg_Vd_arrangement_sz_Q___2S_00__4S_01__2D_11:
  1457  		Rd := x & (1<<5 - 1)
  1458  		sz := (x >> 22) & 1
  1459  		Q := (x >> 30) & 1
  1460  		if sz == 0 && Q == 0 {
  1461  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1462  		} else if sz == 0 && Q == 1 {
  1463  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1464  		} else if sz == 1 && Q == 1 {
  1465  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2D, 0}
  1466  		}
  1467  		return nil
  1468  
  1469  	case arg_Vd_arrangement_sz_Q___2S_10__4S_11:
  1470  		Rd := x & (1<<5 - 1)
  1471  		sz := (x >> 22) & 1
  1472  		Q := (x >> 30) & 1
  1473  		if sz == 1 && Q == 0 {
  1474  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1475  		} else if sz == 1 && Q == 1 {
  1476  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1477  		}
  1478  		return nil
  1479  
  1480  	case arg_Vd_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
  1481  		Rd := x & (1<<5 - 1)
  1482  		sz := (x >> 22) & 1
  1483  		Q := (x >> 30) & 1
  1484  		if sz == 0 && Q == 0 {
  1485  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4H, 0}
  1486  		} else if sz == 0 && Q == 1 {
  1487  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement8H, 0}
  1488  		} else if sz == 1 && Q == 0 {
  1489  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement2S, 0}
  1490  		} else /* sz == 1 && Q == 1 */ {
  1491  			return RegisterWithArrangement{V0 + Reg(Rd), Arrangement4S, 0}
  1492  		}
  1493  
  1494  	case arg_Vm_22_1__S_0__D_1:
  1495  		sz := (x >> 22) & 1
  1496  		Rm := (x >> 16) & (1<<5 - 1)
  1497  		if sz == 0 {
  1498  			return S0 + Reg(Rm)
  1499  		} else {
  1500  			return D0 + Reg(Rm)
  1501  		}
  1502  
  1503  	case arg_Vm_22_2__B_0__H_1__S_2__D_3:
  1504  		size := (x >> 22) & (1<<2 - 1)
  1505  		Rm := (x >> 16) & (1<<5 - 1)
  1506  		if size == 0 {
  1507  			return B0 + Reg(Rm)
  1508  		} else if size == 1 {
  1509  			return H0 + Reg(Rm)
  1510  		} else if size == 2 {
  1511  			return S0 + Reg(Rm)
  1512  		} else {
  1513  			return D0 + Reg(Rm)
  1514  		}
  1515  
  1516  	case arg_Vm_22_2__D_3:
  1517  		size := (x >> 22) & (1<<2 - 1)
  1518  		Rm := (x >> 16) & (1<<5 - 1)
  1519  		if size == 3 {
  1520  			return D0 + Reg(Rm)
  1521  		} else {
  1522  			return nil
  1523  		}
  1524  
  1525  	case arg_Vm_22_2__H_1__S_2:
  1526  		size := (x >> 22) & (1<<2 - 1)
  1527  		Rm := (x >> 16) & (1<<5 - 1)
  1528  		if size == 1 {
  1529  			return H0 + Reg(Rm)
  1530  		} else if size == 2 {
  1531  			return S0 + Reg(Rm)
  1532  		} else {
  1533  			return nil
  1534  		}
  1535  
  1536  	case arg_Vm_arrangement_4S:
  1537  		Rm := (x >> 16) & (1<<5 - 1)
  1538  		return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1539  
  1540  	case arg_Vm_arrangement_Q___8B_0__16B_1:
  1541  		Rm := (x >> 16) & (1<<5 - 1)
  1542  		Q := (x >> 30) & 1
  1543  		if Q == 0 {
  1544  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1545  		} else {
  1546  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1547  		}
  1548  
  1549  	case arg_Vm_arrangement_size___8H_0__4S_1__2D_2:
  1550  		Rm := (x >> 16) & (1<<5 - 1)
  1551  		size := (x >> 22) & 3
  1552  		if size == 0 {
  1553  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1554  		} else if size == 1 {
  1555  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1556  		} else if size == 2 {
  1557  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1558  		}
  1559  		return nil
  1560  
  1561  	case arg_Vm_arrangement_size___H_1__S_2_index__size_L_H_M__HLM_1__HL_2_1:
  1562  		var a Arrangement
  1563  		var index uint32
  1564  		var vm uint32
  1565  		Rm := (x >> 16) & (1<<4 - 1)
  1566  		size := (x >> 22) & 3
  1567  		H := (x >> 11) & 1
  1568  		L := (x >> 21) & 1
  1569  		M := (x >> 20) & 1
  1570  		if size == 1 {
  1571  			a = ArrangementH
  1572  			index = (H << 2) | (L << 1) | M
  1573  			vm = Rm
  1574  		} else if size == 2 {
  1575  			a = ArrangementS
  1576  			index = (H << 1) | L
  1577  			vm = (M << 4) | Rm
  1578  		} else {
  1579  			return nil
  1580  		}
  1581  		return RegisterWithArrangementAndIndex{V0 + Reg(vm), a, uint8(index), 0}
  1582  
  1583  	case arg_Vm_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  1584  		Rm := (x >> 16) & (1<<5 - 1)
  1585  		size := (x >> 22) & 3
  1586  		Q := (x >> 30) & 1
  1587  		if size == 1 && Q == 0 {
  1588  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1589  		} else if size == 1 && Q == 1 {
  1590  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1591  		} else if size == 2 && Q == 0 {
  1592  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1593  		} else if size == 2 && Q == 1 {
  1594  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1595  		}
  1596  		return nil
  1597  
  1598  	case arg_Vm_arrangement_size_Q___8B_00__16B_01:
  1599  		Rm := (x >> 16) & (1<<5 - 1)
  1600  		size := (x >> 22) & 3
  1601  		Q := (x >> 30) & 1
  1602  		if size == 0 && Q == 0 {
  1603  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1604  		} else if size == 0 && Q == 1 {
  1605  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1606  		}
  1607  		return nil
  1608  
  1609  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
  1610  		Rm := (x >> 16) & (1<<5 - 1)
  1611  		size := (x >> 22) & 3
  1612  		Q := (x >> 30) & 1
  1613  		if size == 0 && Q == 0 {
  1614  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1615  		} else if size == 0 && Q == 1 {
  1616  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1617  		} else if size == 3 && Q == 0 {
  1618  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement1D, 0}
  1619  		} else if size == 3 && Q == 1 {
  1620  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1621  		}
  1622  		return nil
  1623  
  1624  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  1625  		Rm := (x >> 16) & (1<<5 - 1)
  1626  		size := (x >> 22) & 3
  1627  		Q := (x >> 30) & 1
  1628  		if size == 0 && Q == 0 {
  1629  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1630  		} else if size == 0 && Q == 1 {
  1631  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1632  		} else if size == 1 && Q == 0 {
  1633  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1634  		} else if size == 1 && Q == 1 {
  1635  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1636  		} else if size == 2 && Q == 0 {
  1637  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1638  		} else if size == 2 && Q == 1 {
  1639  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1640  		}
  1641  		return nil
  1642  
  1643  	case arg_Vm_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  1644  		Rm := (x >> 16) & (1<<5 - 1)
  1645  		size := (x >> 22) & 3
  1646  		Q := (x >> 30) & 1
  1647  		if size == 0 && Q == 0 {
  1648  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8B, 0}
  1649  		} else if size == 0 && Q == 1 {
  1650  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement16B, 0}
  1651  		} else if size == 1 && Q == 0 {
  1652  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4H, 0}
  1653  		} else if size == 1 && Q == 1 {
  1654  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement8H, 0}
  1655  		} else if size == 2 && Q == 0 {
  1656  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1657  		} else if size == 2 && Q == 1 {
  1658  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1659  		} else if size == 3 && Q == 1 {
  1660  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1661  		}
  1662  		return nil
  1663  
  1664  	case arg_Vm_arrangement_sz_Q___2S_00__4S_01__2D_11:
  1665  		Rm := (x >> 16) & (1<<5 - 1)
  1666  		sz := (x >> 22) & 1
  1667  		Q := (x >> 30) & 1
  1668  		if sz == 0 && Q == 0 {
  1669  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2S, 0}
  1670  		} else if sz == 0 && Q == 1 {
  1671  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement4S, 0}
  1672  		} else if sz == 1 && Q == 1 {
  1673  			return RegisterWithArrangement{V0 + Reg(Rm), Arrangement2D, 0}
  1674  		}
  1675  		return nil
  1676  
  1677  	case arg_Vm_arrangement_sz___S_0__D_1_index__sz_L_H__HL_00__H_10_1:
  1678  		var a Arrangement
  1679  		var index uint32
  1680  		Rm := (x >> 16) & (1<<5 - 1)
  1681  		sz := (x >> 22) & 1
  1682  		H := (x >> 11) & 1
  1683  		L := (x >> 21) & 1
  1684  		if sz == 0 {
  1685  			a = ArrangementS
  1686  			index = (H << 1) | L
  1687  		} else if sz == 1 && L == 0 {
  1688  			a = ArrangementD
  1689  			index = H
  1690  		} else {
  1691  			return nil
  1692  		}
  1693  		return RegisterWithArrangementAndIndex{V0 + Reg(Rm), a, uint8(index), 0}
  1694  
  1695  	case arg_Vn_19_4__B_1__H_2__S_4__D_8:
  1696  		immh := (x >> 19) & (1<<4 - 1)
  1697  		Rn := (x >> 5) & (1<<5 - 1)
  1698  		if immh == 1 {
  1699  			return B0 + Reg(Rn)
  1700  		} else if immh>>1 == 1 {
  1701  			return H0 + Reg(Rn)
  1702  		} else if immh>>2 == 1 {
  1703  			return S0 + Reg(Rn)
  1704  		} else if immh>>3 == 1 {
  1705  			return D0 + Reg(Rn)
  1706  		} else {
  1707  			return nil
  1708  		}
  1709  
  1710  	case arg_Vn_19_4__D_8:
  1711  		immh := (x >> 19) & (1<<4 - 1)
  1712  		Rn := (x >> 5) & (1<<5 - 1)
  1713  		if immh>>3 == 1 {
  1714  			return D0 + Reg(Rn)
  1715  		} else {
  1716  			return nil
  1717  		}
  1718  
  1719  	case arg_Vn_19_4__H_1__S_2__D_4:
  1720  		immh := (x >> 19) & (1<<4 - 1)
  1721  		Rn := (x >> 5) & (1<<5 - 1)
  1722  		if immh == 1 {
  1723  			return H0 + Reg(Rn)
  1724  		} else if immh>>1 == 1 {
  1725  			return S0 + Reg(Rn)
  1726  		} else if immh>>2 == 1 {
  1727  			return D0 + Reg(Rn)
  1728  		} else {
  1729  			return nil
  1730  		}
  1731  
  1732  	case arg_Vn_19_4__S_4__D_8:
  1733  		immh := (x >> 19) & (1<<4 - 1)
  1734  		Rn := (x >> 5) & (1<<5 - 1)
  1735  		if immh>>2 == 1 {
  1736  			return S0 + Reg(Rn)
  1737  		} else if immh>>3 == 1 {
  1738  			return D0 + Reg(Rn)
  1739  		} else {
  1740  			return nil
  1741  		}
  1742  
  1743  	case arg_Vn_1_arrangement_16B:
  1744  		Rn := (x >> 5) & (1<<5 - 1)
  1745  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 1}
  1746  
  1747  	case arg_Vn_22_1__D_1:
  1748  		sz := (x >> 22) & 1
  1749  		Rn := (x >> 5) & (1<<5 - 1)
  1750  		if sz == 1 {
  1751  			return D0 + Reg(Rn)
  1752  		}
  1753  		return nil
  1754  
  1755  	case arg_Vn_22_1__S_0__D_1:
  1756  		sz := (x >> 22) & 1
  1757  		Rn := (x >> 5) & (1<<5 - 1)
  1758  		if sz == 0 {
  1759  			return S0 + Reg(Rn)
  1760  		} else {
  1761  			return D0 + Reg(Rn)
  1762  		}
  1763  
  1764  	case arg_Vn_22_2__B_0__H_1__S_2__D_3:
  1765  		size := (x >> 22) & (1<<2 - 1)
  1766  		Rn := (x >> 5) & (1<<5 - 1)
  1767  		if size == 0 {
  1768  			return B0 + Reg(Rn)
  1769  		} else if size == 1 {
  1770  			return H0 + Reg(Rn)
  1771  		} else if size == 2 {
  1772  			return S0 + Reg(Rn)
  1773  		} else {
  1774  			return D0 + Reg(Rn)
  1775  		}
  1776  
  1777  	case arg_Vn_22_2__D_3:
  1778  		size := (x >> 22) & (1<<2 - 1)
  1779  		Rn := (x >> 5) & (1<<5 - 1)
  1780  		if size == 3 {
  1781  			return D0 + Reg(Rn)
  1782  		} else {
  1783  			return nil
  1784  		}
  1785  
  1786  	case arg_Vn_22_2__H_0__S_1__D_2:
  1787  		size := (x >> 22) & (1<<2 - 1)
  1788  		Rn := (x >> 5) & (1<<5 - 1)
  1789  		if size == 0 {
  1790  			return H0 + Reg(Rn)
  1791  		} else if size == 1 {
  1792  			return S0 + Reg(Rn)
  1793  		} else if size == 2 {
  1794  			return D0 + Reg(Rn)
  1795  		} else {
  1796  			return nil
  1797  		}
  1798  
  1799  	case arg_Vn_22_2__H_1__S_2:
  1800  		size := (x >> 22) & (1<<2 - 1)
  1801  		Rn := (x >> 5) & (1<<5 - 1)
  1802  		if size == 1 {
  1803  			return H0 + Reg(Rn)
  1804  		} else if size == 2 {
  1805  			return S0 + Reg(Rn)
  1806  		} else {
  1807  			return nil
  1808  		}
  1809  
  1810  	case arg_Vn_2_arrangement_16B:
  1811  		Rn := (x >> 5) & (1<<5 - 1)
  1812  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 2}
  1813  
  1814  	case arg_Vn_3_arrangement_16B:
  1815  		Rn := (x >> 5) & (1<<5 - 1)
  1816  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 3}
  1817  
  1818  	case arg_Vn_4_arrangement_16B:
  1819  		Rn := (x >> 5) & (1<<5 - 1)
  1820  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 4}
  1821  
  1822  	case arg_Vn_arrangement_16B:
  1823  		Rn := (x >> 5) & (1<<5 - 1)
  1824  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1825  
  1826  	case arg_Vn_arrangement_4S:
  1827  		Rn := (x >> 5) & (1<<5 - 1)
  1828  		return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1829  
  1830  	case arg_Vn_arrangement_D_index__1:
  1831  		Rn := (x >> 5) & (1<<5 - 1)
  1832  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, 1, 0}
  1833  
  1834  	case arg_Vn_arrangement_D_index__imm5_1:
  1835  		Rn := (x >> 5) & (1<<5 - 1)
  1836  		index := (x >> 20) & 1
  1837  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementD, uint8(index), 0}
  1838  
  1839  	case arg_Vn_arrangement_imm5___B_1__H_2_index__imm5__imm5lt41gt_1__imm5lt42gt_2_1:
  1840  		var a Arrangement
  1841  		var index uint32
  1842  		Rn := (x >> 5) & (1<<5 - 1)
  1843  		imm5 := (x >> 16) & (1<<5 - 1)
  1844  		if imm5&1 == 1 {
  1845  			a = ArrangementB
  1846  			index = imm5 >> 1
  1847  		} else if imm5&2 == 2 {
  1848  			a = ArrangementH
  1849  			index = imm5 >> 2
  1850  		} else {
  1851  			return nil
  1852  		}
  1853  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1854  
  1855  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5_imm4__imm4lt30gt_1__imm4lt31gt_2__imm4lt32gt_4__imm4lt3gt_8_1:
  1856  		var a Arrangement
  1857  		var index uint32
  1858  		Rn := (x >> 5) & (1<<5 - 1)
  1859  		imm5 := (x >> 16) & (1<<5 - 1)
  1860  		imm4 := (x >> 11) & (1<<4 - 1)
  1861  		if imm5&1 == 1 {
  1862  			a = ArrangementB
  1863  			index = imm4
  1864  		} else if imm5&2 == 2 {
  1865  			a = ArrangementH
  1866  			index = imm4 >> 1
  1867  		} else if imm5&4 == 4 {
  1868  			a = ArrangementS
  1869  			index = imm4 >> 2
  1870  		} else if imm5&8 == 8 {
  1871  			a = ArrangementD
  1872  			index = imm4 >> 3
  1873  		} else {
  1874  			return nil
  1875  		}
  1876  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1877  
  1878  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4__D_8_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4__imm5lt4gt_8_1:
  1879  		var a Arrangement
  1880  		var index uint32
  1881  		Rn := (x >> 5) & (1<<5 - 1)
  1882  		imm5 := (x >> 16) & (1<<5 - 1)
  1883  		if imm5&1 == 1 {
  1884  			a = ArrangementB
  1885  			index = imm5 >> 1
  1886  		} else if imm5&2 == 2 {
  1887  			a = ArrangementH
  1888  			index = imm5 >> 2
  1889  		} else if imm5&4 == 4 {
  1890  			a = ArrangementS
  1891  			index = imm5 >> 3
  1892  		} else if imm5&8 == 8 {
  1893  			a = ArrangementD
  1894  			index = imm5 >> 4
  1895  		} else {
  1896  			return nil
  1897  		}
  1898  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1899  
  1900  	case arg_Vn_arrangement_imm5___B_1__H_2__S_4_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
  1901  		var a Arrangement
  1902  		var index uint32
  1903  		Rn := (x >> 5) & (1<<5 - 1)
  1904  		imm5 := (x >> 16) & (1<<5 - 1)
  1905  		if imm5&1 == 1 {
  1906  			a = ArrangementB
  1907  			index = imm5 >> 1
  1908  		} else if imm5&2 == 2 {
  1909  			a = ArrangementH
  1910  			index = imm5 >> 2
  1911  		} else if imm5&4 == 4 {
  1912  			a = ArrangementS
  1913  			index = imm5 >> 3
  1914  		} else {
  1915  			return nil
  1916  		}
  1917  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1918  
  1919  	case arg_Vn_arrangement_imm5___D_8_index__imm5_1:
  1920  		var a Arrangement
  1921  		var index uint32
  1922  		Rn := (x >> 5) & (1<<5 - 1)
  1923  		imm5 := (x >> 16) & (1<<5 - 1)
  1924  		if imm5&15 == 8 {
  1925  			a = ArrangementD
  1926  			index = imm5 >> 4
  1927  		} else {
  1928  			return nil
  1929  		}
  1930  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), a, uint8(index), 0}
  1931  
  1932  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__2S_40__4S_41__2D_81:
  1933  		Rn := (x >> 5) & (1<<5 - 1)
  1934  		immh := (x >> 19) & (1<<4 - 1)
  1935  		Q := (x >> 30) & 1
  1936  		if immh>>2 == 1 {
  1937  			if Q == 0 {
  1938  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1939  			} else {
  1940  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1941  			}
  1942  		} else if immh>>3 == 1 {
  1943  			if Q == 1 {
  1944  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  1945  			}
  1946  		}
  1947  		return nil
  1948  
  1949  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41:
  1950  		Rn := (x >> 5) & (1<<5 - 1)
  1951  		immh := (x >> 19) & (1<<4 - 1)
  1952  		Q := (x >> 30) & 1
  1953  		if immh == 1 {
  1954  			if Q == 0 {
  1955  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  1956  			} else {
  1957  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1958  			}
  1959  		} else if immh>>1 == 1 {
  1960  			if Q == 0 {
  1961  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  1962  			} else {
  1963  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  1964  			}
  1965  		} else if immh>>2 == 1 {
  1966  			if Q == 0 {
  1967  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1968  			} else {
  1969  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1970  			}
  1971  		}
  1972  		return nil
  1973  
  1974  	case arg_Vn_arrangement_immh_Q___SEEAdvancedSIMDmodifiedimmediate_00__8B_10__16B_11__4H_20__8H_21__2S_40__4S_41__2D_81:
  1975  		Rn := (x >> 5) & (1<<5 - 1)
  1976  		immh := (x >> 19) & (1<<4 - 1)
  1977  		Q := (x >> 30) & 1
  1978  		if immh == 1 {
  1979  			if Q == 0 {
  1980  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  1981  			} else {
  1982  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  1983  			}
  1984  		} else if immh>>1 == 1 {
  1985  			if Q == 0 {
  1986  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  1987  			} else {
  1988  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  1989  			}
  1990  		} else if immh>>2 == 1 {
  1991  			if Q == 0 {
  1992  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  1993  			} else {
  1994  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  1995  			}
  1996  		} else if immh>>3 == 1 {
  1997  			if Q == 1 {
  1998  				return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  1999  			}
  2000  		}
  2001  		return nil
  2002  
  2003  	case arg_Vn_arrangement_immh___SEEAdvancedSIMDmodifiedimmediate_0__8H_1__4S_2__2D_4:
  2004  		Rn := (x >> 5) & (1<<5 - 1)
  2005  		immh := (x >> 19) & (1<<4 - 1)
  2006  		if immh == 1 {
  2007  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2008  		} else if immh>>1 == 1 {
  2009  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2010  		} else if immh>>2 == 1 {
  2011  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2012  		}
  2013  		return nil
  2014  
  2015  	case arg_Vn_arrangement_Q___8B_0__16B_1:
  2016  		Rn := (x >> 5) & (1<<5 - 1)
  2017  		Q := (x >> 30) & 1
  2018  		if Q == 0 {
  2019  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2020  		} else {
  2021  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2022  		}
  2023  
  2024  	case arg_Vn_arrangement_Q_sz___2S_00__4S_10__2D_11:
  2025  		Rn := (x >> 5) & (1<<5 - 1)
  2026  		Q := (x >> 30) & 1
  2027  		sz := (x >> 22) & 1
  2028  		if sz == 0 && Q == 0 {
  2029  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2030  		} else if sz == 0 && Q == 1 {
  2031  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2032  		} else if sz == 1 && Q == 1 {
  2033  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2034  		}
  2035  		return nil
  2036  
  2037  	case arg_Vn_arrangement_Q_sz___4S_10:
  2038  		Rn := (x >> 5) & (1<<5 - 1)
  2039  		Q := (x >> 30) & 1
  2040  		sz := (x >> 22) & 1
  2041  		if sz == 0 && Q == 1 {
  2042  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2043  		}
  2044  		return nil
  2045  
  2046  	case arg_Vn_arrangement_S_index__imm5__imm5lt41gt_1__imm5lt42gt_2__imm5lt43gt_4_1:
  2047  		var index uint32
  2048  		Rn := (x >> 5) & (1<<5 - 1)
  2049  		imm5 := (x >> 16) & (1<<5 - 1)
  2050  		index = imm5 >> 3
  2051  		return RegisterWithArrangementAndIndex{V0 + Reg(Rn), ArrangementS, uint8(index), 0}
  2052  
  2053  	case arg_Vn_arrangement_size___2D_3:
  2054  		Rn := (x >> 5) & (1<<5 - 1)
  2055  		size := (x >> 22) & 3
  2056  		if size == 3 {
  2057  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2058  		}
  2059  		return nil
  2060  
  2061  	case arg_Vn_arrangement_size___8H_0__4S_1__2D_2:
  2062  		Rn := (x >> 5) & (1<<5 - 1)
  2063  		size := (x >> 22) & 3
  2064  		if size == 0 {
  2065  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2066  		} else if size == 1 {
  2067  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2068  		} else if size == 2 {
  2069  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2070  		}
  2071  		return nil
  2072  
  2073  	case arg_Vn_arrangement_size_Q___4H_10__8H_11__2S_20__4S_21:
  2074  		Rn := (x >> 5) & (1<<5 - 1)
  2075  		size := (x >> 22) & 3
  2076  		Q := (x >> 30) & 1
  2077  		if size == 1 && Q == 0 {
  2078  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2079  		} else if size == 1 && Q == 1 {
  2080  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2081  		} else if size == 2 && Q == 0 {
  2082  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2083  		} else if size == 2 && Q == 1 {
  2084  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2085  		}
  2086  		return nil
  2087  
  2088  	case arg_Vn_arrangement_size_Q___8B_00__16B_01:
  2089  		Rn := (x >> 5) & (1<<5 - 1)
  2090  		size := (x >> 22) & 3
  2091  		Q := (x >> 30) & 1
  2092  		if size == 0 && Q == 0 {
  2093  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2094  		} else if size == 0 && Q == 1 {
  2095  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2096  		}
  2097  		return nil
  2098  
  2099  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__1D_30__2D_31:
  2100  		Rn := (x >> 5) & (1<<5 - 1)
  2101  		size := (x >> 22) & 3
  2102  		Q := (x >> 30) & 1
  2103  		if size == 0 && Q == 0 {
  2104  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2105  		} else if size == 0 && Q == 1 {
  2106  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2107  		} else if size == 3 && Q == 0 {
  2108  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement1D, 0}
  2109  		} else if size == 3 && Q == 1 {
  2110  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2111  		}
  2112  		return nil
  2113  
  2114  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11:
  2115  		Rn := (x >> 5) & (1<<5 - 1)
  2116  		size := (x >> 22) & 3
  2117  		Q := (x >> 30) & 1
  2118  		if size == 0 && Q == 0 {
  2119  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2120  		} else if size == 0 && Q == 1 {
  2121  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2122  		} else if size == 1 && Q == 0 {
  2123  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2124  		} else if size == 1 && Q == 1 {
  2125  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2126  		}
  2127  		return nil
  2128  
  2129  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21:
  2130  		Rn := (x >> 5) & (1<<5 - 1)
  2131  		size := (x >> 22) & 3
  2132  		Q := (x >> 30) & 1
  2133  		if size == 0 && Q == 0 {
  2134  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2135  		} else if size == 0 && Q == 1 {
  2136  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2137  		} else if size == 1 && Q == 0 {
  2138  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2139  		} else if size == 1 && Q == 1 {
  2140  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2141  		} else if size == 2 && Q == 0 {
  2142  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2143  		} else if size == 2 && Q == 1 {
  2144  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2145  		}
  2146  		return nil
  2147  
  2148  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2149  		Rn := (x >> 5) & (1<<5 - 1)
  2150  		size := (x >> 22) & 3
  2151  		Q := (x >> 30) & 1
  2152  		if size == 0 && Q == 0 {
  2153  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2154  		} else if size == 0 && Q == 1 {
  2155  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2156  		} else if size == 1 && Q == 0 {
  2157  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2158  		} else if size == 1 && Q == 1 {
  2159  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2160  		} else if size == 2 && Q == 0 {
  2161  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2162  		} else if size == 2 && Q == 1 {
  2163  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2164  		} else if size == 3 && Q == 1 {
  2165  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2166  		}
  2167  		return nil
  2168  
  2169  	case arg_Vn_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__4S_21:
  2170  		Rn := (x >> 5) & (1<<5 - 1)
  2171  		size := (x >> 22) & 3
  2172  		Q := (x >> 30) & 1
  2173  		if size == 0 && Q == 0 {
  2174  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8B, 0}
  2175  		} else if size == 0 && Q == 1 {
  2176  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement16B, 0}
  2177  		} else if size == 1 && Q == 0 {
  2178  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2179  		} else if size == 1 && Q == 1 {
  2180  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2181  		} else if size == 2 && Q == 1 {
  2182  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2183  		}
  2184  		return nil
  2185  
  2186  	case arg_Vn_arrangement_sz___2D_1:
  2187  		Rn := (x >> 5) & (1<<5 - 1)
  2188  		sz := (x >> 22) & 1
  2189  		if sz == 1 {
  2190  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2191  		}
  2192  		return nil
  2193  
  2194  	case arg_Vn_arrangement_sz___2S_0__2D_1:
  2195  		Rn := (x >> 5) & (1<<5 - 1)
  2196  		sz := (x >> 22) & 1
  2197  		if sz == 0 {
  2198  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2199  		} else {
  2200  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2201  		}
  2202  
  2203  	case arg_Vn_arrangement_sz___4S_0__2D_1:
  2204  		Rn := (x >> 5) & (1<<5 - 1)
  2205  		sz := (x >> 22) & 1
  2206  		if sz == 0 {
  2207  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2208  		} else {
  2209  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2210  		}
  2211  
  2212  	case arg_Vn_arrangement_sz_Q___2S_00__4S_01:
  2213  		Rn := (x >> 5) & (1<<5 - 1)
  2214  		sz := (x >> 22) & 1
  2215  		Q := (x >> 30) & 1
  2216  		if sz == 0 && Q == 0 {
  2217  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2218  		} else if sz == 0 && Q == 1 {
  2219  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2220  		}
  2221  		return nil
  2222  
  2223  	case arg_Vn_arrangement_sz_Q___2S_00__4S_01__2D_11:
  2224  		Rn := (x >> 5) & (1<<5 - 1)
  2225  		sz := (x >> 22) & 1
  2226  		Q := (x >> 30) & 1
  2227  		if sz == 0 && Q == 0 {
  2228  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2229  		} else if sz == 0 && Q == 1 {
  2230  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2231  		} else if sz == 1 && Q == 1 {
  2232  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2D, 0}
  2233  		}
  2234  		return nil
  2235  
  2236  	case arg_Vn_arrangement_sz_Q___4H_00__8H_01__2S_10__4S_11:
  2237  		Rn := (x >> 5) & (1<<5 - 1)
  2238  		sz := (x >> 22) & 1
  2239  		Q := (x >> 30) & 1
  2240  		if sz == 0 && Q == 0 {
  2241  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4H, 0}
  2242  		} else if sz == 0 && Q == 1 {
  2243  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement8H, 0}
  2244  		} else if sz == 1 && Q == 0 {
  2245  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement2S, 0}
  2246  		} else /* sz == 1 && Q == 1 */ {
  2247  			return RegisterWithArrangement{V0 + Reg(Rn), Arrangement4S, 0}
  2248  		}
  2249  
  2250  	case arg_Vt_1_arrangement_B_index__Q_S_size_1:
  2251  		Rt := x & (1<<5 - 1)
  2252  		Q := (x >> 30) & 1
  2253  		S := (x >> 12) & 1
  2254  		size := (x >> 10) & 3
  2255  		index := (Q << 3) | (S << 2) | (size)
  2256  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 1}
  2257  
  2258  	case arg_Vt_1_arrangement_D_index__Q_1:
  2259  		Rt := x & (1<<5 - 1)
  2260  		index := (x >> 30) & 1
  2261  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 1}
  2262  
  2263  	case arg_Vt_1_arrangement_H_index__Q_S_size_1:
  2264  		Rt := x & (1<<5 - 1)
  2265  		Q := (x >> 30) & 1
  2266  		S := (x >> 12) & 1
  2267  		size := (x >> 11) & 1
  2268  		index := (Q << 2) | (S << 1) | (size)
  2269  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 1}
  2270  
  2271  	case arg_Vt_1_arrangement_S_index__Q_S_1:
  2272  		Rt := x & (1<<5 - 1)
  2273  		Q := (x >> 30) & 1
  2274  		S := (x >> 12) & 1
  2275  		index := (Q << 1) | S
  2276  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 1}
  2277  
  2278  	case arg_Vt_1_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2279  		Rt := x & (1<<5 - 1)
  2280  		Q := (x >> 30) & 1
  2281  		size := (x >> 10) & 3
  2282  		if size == 0 && Q == 0 {
  2283  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 1}
  2284  		} else if size == 0 && Q == 1 {
  2285  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 1}
  2286  		} else if size == 1 && Q == 0 {
  2287  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 1}
  2288  		} else if size == 1 && Q == 1 {
  2289  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 1}
  2290  		} else if size == 2 && Q == 0 {
  2291  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 1}
  2292  		} else if size == 2 && Q == 1 {
  2293  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 1}
  2294  		} else if size == 3 && Q == 0 {
  2295  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 1}
  2296  		} else /* size == 3 && Q == 1 */ {
  2297  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 1}
  2298  		}
  2299  
  2300  	case arg_Vt_2_arrangement_B_index__Q_S_size_1:
  2301  		Rt := x & (1<<5 - 1)
  2302  		Q := (x >> 30) & 1
  2303  		S := (x >> 12) & 1
  2304  		size := (x >> 10) & 3
  2305  		index := (Q << 3) | (S << 2) | (size)
  2306  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 2}
  2307  
  2308  	case arg_Vt_2_arrangement_D_index__Q_1:
  2309  		Rt := x & (1<<5 - 1)
  2310  		index := (x >> 30) & 1
  2311  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 2}
  2312  
  2313  	case arg_Vt_2_arrangement_H_index__Q_S_size_1:
  2314  		Rt := x & (1<<5 - 1)
  2315  		Q := (x >> 30) & 1
  2316  		S := (x >> 12) & 1
  2317  		size := (x >> 11) & 1
  2318  		index := (Q << 2) | (S << 1) | (size)
  2319  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 2}
  2320  
  2321  	case arg_Vt_2_arrangement_S_index__Q_S_1:
  2322  		Rt := x & (1<<5 - 1)
  2323  		Q := (x >> 30) & 1
  2324  		S := (x >> 12) & 1
  2325  		index := (Q << 1) | S
  2326  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 2}
  2327  
  2328  	case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2329  		Rt := x & (1<<5 - 1)
  2330  		Q := (x >> 30) & 1
  2331  		size := (x >> 10) & 3
  2332  		if size == 0 && Q == 0 {
  2333  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
  2334  		} else if size == 0 && Q == 1 {
  2335  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
  2336  		} else if size == 1 && Q == 0 {
  2337  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
  2338  		} else if size == 1 && Q == 1 {
  2339  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
  2340  		} else if size == 2 && Q == 0 {
  2341  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
  2342  		} else if size == 2 && Q == 1 {
  2343  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
  2344  		} else if size == 3 && Q == 0 {
  2345  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 2}
  2346  		} else /* size == 3 && Q == 1 */ {
  2347  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
  2348  		}
  2349  
  2350  	case arg_Vt_2_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2351  		Rt := x & (1<<5 - 1)
  2352  		Q := (x >> 30) & 1
  2353  		size := (x >> 10) & 3
  2354  		if size == 0 && Q == 0 {
  2355  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 2}
  2356  		} else if size == 0 && Q == 1 {
  2357  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 2}
  2358  		} else if size == 1 && Q == 0 {
  2359  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 2}
  2360  		} else if size == 1 && Q == 1 {
  2361  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 2}
  2362  		} else if size == 2 && Q == 0 {
  2363  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 2}
  2364  		} else if size == 2 && Q == 1 {
  2365  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 2}
  2366  		} else if size == 3 && Q == 1 {
  2367  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 2}
  2368  		}
  2369  		return nil
  2370  
  2371  	case arg_Vt_3_arrangement_B_index__Q_S_size_1:
  2372  		Rt := x & (1<<5 - 1)
  2373  		Q := (x >> 30) & 1
  2374  		S := (x >> 12) & 1
  2375  		size := (x >> 10) & 3
  2376  		index := (Q << 3) | (S << 2) | (size)
  2377  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 3}
  2378  
  2379  	case arg_Vt_3_arrangement_D_index__Q_1:
  2380  		Rt := x & (1<<5 - 1)
  2381  		index := (x >> 30) & 1
  2382  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 3}
  2383  
  2384  	case arg_Vt_3_arrangement_H_index__Q_S_size_1:
  2385  		Rt := x & (1<<5 - 1)
  2386  		Q := (x >> 30) & 1
  2387  		S := (x >> 12) & 1
  2388  		size := (x >> 11) & 1
  2389  		index := (Q << 2) | (S << 1) | (size)
  2390  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 3}
  2391  
  2392  	case arg_Vt_3_arrangement_S_index__Q_S_1:
  2393  		Rt := x & (1<<5 - 1)
  2394  		Q := (x >> 30) & 1
  2395  		S := (x >> 12) & 1
  2396  		index := (Q << 1) | S
  2397  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 3}
  2398  
  2399  	case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2400  		Rt := x & (1<<5 - 1)
  2401  		Q := (x >> 30) & 1
  2402  		size := (x >> 10) & 3
  2403  		if size == 0 && Q == 0 {
  2404  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
  2405  		} else if size == 0 && Q == 1 {
  2406  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
  2407  		} else if size == 1 && Q == 0 {
  2408  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
  2409  		} else if size == 1 && Q == 1 {
  2410  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
  2411  		} else if size == 2 && Q == 0 {
  2412  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
  2413  		} else if size == 2 && Q == 1 {
  2414  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
  2415  		} else if size == 3 && Q == 0 {
  2416  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 3}
  2417  		} else /* size == 3 && Q == 1 */ {
  2418  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
  2419  		}
  2420  
  2421  	case arg_Vt_3_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2422  		Rt := x & (1<<5 - 1)
  2423  		Q := (x >> 30) & 1
  2424  		size := (x >> 10) & 3
  2425  		if size == 0 && Q == 0 {
  2426  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 3}
  2427  		} else if size == 0 && Q == 1 {
  2428  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 3}
  2429  		} else if size == 1 && Q == 0 {
  2430  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 3}
  2431  		} else if size == 1 && Q == 1 {
  2432  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 3}
  2433  		} else if size == 2 && Q == 0 {
  2434  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 3}
  2435  		} else if size == 2 && Q == 1 {
  2436  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 3}
  2437  		} else if size == 3 && Q == 1 {
  2438  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 3}
  2439  		}
  2440  		return nil
  2441  
  2442  	case arg_Vt_4_arrangement_B_index__Q_S_size_1:
  2443  		Rt := x & (1<<5 - 1)
  2444  		Q := (x >> 30) & 1
  2445  		S := (x >> 12) & 1
  2446  		size := (x >> 10) & 3
  2447  		index := (Q << 3) | (S << 2) | (size)
  2448  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementB, uint8(index), 4}
  2449  
  2450  	case arg_Vt_4_arrangement_D_index__Q_1:
  2451  		Rt := x & (1<<5 - 1)
  2452  		index := (x >> 30) & 1
  2453  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementD, uint8(index), 4}
  2454  
  2455  	case arg_Vt_4_arrangement_H_index__Q_S_size_1:
  2456  		Rt := x & (1<<5 - 1)
  2457  		Q := (x >> 30) & 1
  2458  		S := (x >> 12) & 1
  2459  		size := (x >> 11) & 1
  2460  		index := (Q << 2) | (S << 1) | (size)
  2461  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementH, uint8(index), 4}
  2462  
  2463  	case arg_Vt_4_arrangement_S_index__Q_S_1:
  2464  		Rt := x & (1<<5 - 1)
  2465  		Q := (x >> 30) & 1
  2466  		S := (x >> 12) & 1
  2467  		index := (Q << 1) | S
  2468  		return RegisterWithArrangementAndIndex{V0 + Reg(Rt), ArrangementS, uint8(index), 4}
  2469  
  2470  	case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__1D_30__2D_31:
  2471  		Rt := x & (1<<5 - 1)
  2472  		Q := (x >> 30) & 1
  2473  		size := (x >> 10) & 3
  2474  		if size == 0 && Q == 0 {
  2475  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
  2476  		} else if size == 0 && Q == 1 {
  2477  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
  2478  		} else if size == 1 && Q == 0 {
  2479  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
  2480  		} else if size == 1 && Q == 1 {
  2481  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
  2482  		} else if size == 2 && Q == 0 {
  2483  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
  2484  		} else if size == 2 && Q == 1 {
  2485  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
  2486  		} else if size == 3 && Q == 0 {
  2487  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement1D, 4}
  2488  		} else /* size == 3 && Q == 1 */ {
  2489  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
  2490  		}
  2491  
  2492  	case arg_Vt_4_arrangement_size_Q___8B_00__16B_01__4H_10__8H_11__2S_20__4S_21__2D_31:
  2493  		Rt := x & (1<<5 - 1)
  2494  		Q := (x >> 30) & 1
  2495  		size := (x >> 10) & 3
  2496  		if size == 0 && Q == 0 {
  2497  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8B, 4}
  2498  		} else if size == 0 && Q == 1 {
  2499  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement16B, 4}
  2500  		} else if size == 1 && Q == 0 {
  2501  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4H, 4}
  2502  		} else if size == 1 && Q == 1 {
  2503  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement8H, 4}
  2504  		} else if size == 2 && Q == 0 {
  2505  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2S, 4}
  2506  		} else if size == 2 && Q == 1 {
  2507  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement4S, 4}
  2508  		} else if size == 3 && Q == 1 {
  2509  			return RegisterWithArrangement{V0 + Reg(Rt), Arrangement2D, 4}
  2510  		}
  2511  		return nil
  2512  
  2513  	case arg_Xns_mem_extend_m__UXTW_2__LSL_3__SXTW_6__SXTX_7__0_0__4_1:
  2514  		return handle_MemExtend(x, 4, false)
  2515  
  2516  	case arg_Xns_mem_offset:
  2517  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2518  		return MemImmediate{Rn, AddrOffset, 0}
  2519  
  2520  	case arg_Xns_mem_optional_imm12_16_unsigned:
  2521  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2522  		imm12 := (x >> 10) & (1<<12 - 1)
  2523  		return MemImmediate{Rn, AddrOffset, int32(imm12 << 4)}
  2524  
  2525  	case arg_Xns_mem_optional_imm7_16_signed:
  2526  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2527  		imm7 := (x >> 15) & (1<<7 - 1)
  2528  		return MemImmediate{Rn, AddrOffset, ((int32(imm7 << 4)) << 21) >> 21}
  2529  
  2530  	case arg_Xns_mem_post_fixedimm_1:
  2531  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2532  		return MemImmediate{Rn, AddrPostIndex, 1}
  2533  
  2534  	case arg_Xns_mem_post_fixedimm_12:
  2535  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2536  		return MemImmediate{Rn, AddrPostIndex, 12}
  2537  
  2538  	case arg_Xns_mem_post_fixedimm_16:
  2539  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2540  		return MemImmediate{Rn, AddrPostIndex, 16}
  2541  
  2542  	case arg_Xns_mem_post_fixedimm_2:
  2543  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2544  		return MemImmediate{Rn, AddrPostIndex, 2}
  2545  
  2546  	case arg_Xns_mem_post_fixedimm_24:
  2547  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2548  		return MemImmediate{Rn, AddrPostIndex, 24}
  2549  
  2550  	case arg_Xns_mem_post_fixedimm_3:
  2551  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2552  		return MemImmediate{Rn, AddrPostIndex, 3}
  2553  
  2554  	case arg_Xns_mem_post_fixedimm_32:
  2555  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2556  		return MemImmediate{Rn, AddrPostIndex, 32}
  2557  
  2558  	case arg_Xns_mem_post_fixedimm_4:
  2559  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2560  		return MemImmediate{Rn, AddrPostIndex, 4}
  2561  
  2562  	case arg_Xns_mem_post_fixedimm_6:
  2563  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2564  		return MemImmediate{Rn, AddrPostIndex, 6}
  2565  
  2566  	case arg_Xns_mem_post_fixedimm_8:
  2567  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2568  		return MemImmediate{Rn, AddrPostIndex, 8}
  2569  
  2570  	case arg_Xns_mem_post_imm7_16_signed:
  2571  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2572  		imm7 := (x >> 15) & (1<<7 - 1)
  2573  		return MemImmediate{Rn, AddrPostIndex, ((int32(imm7 << 4)) << 21) >> 21}
  2574  
  2575  	case arg_Xns_mem_post_Q__16_0__32_1:
  2576  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2577  		Q := (x >> 30) & 1
  2578  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 16)}
  2579  
  2580  	case arg_Xns_mem_post_Q__24_0__48_1:
  2581  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2582  		Q := (x >> 30) & 1
  2583  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 24)}
  2584  
  2585  	case arg_Xns_mem_post_Q__32_0__64_1:
  2586  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2587  		Q := (x >> 30) & 1
  2588  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 32)}
  2589  
  2590  	case arg_Xns_mem_post_Q__8_0__16_1:
  2591  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2592  		Q := (x >> 30) & 1
  2593  		return MemImmediate{Rn, AddrPostIndex, int32((Q + 1) * 8)}
  2594  
  2595  	case arg_Xns_mem_post_size__1_0__2_1__4_2__8_3:
  2596  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2597  		size := (x >> 10) & 3
  2598  		return MemImmediate{Rn, AddrPostIndex, int32(1 << size)}
  2599  
  2600  	case arg_Xns_mem_post_size__2_0__4_1__8_2__16_3:
  2601  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2602  		size := (x >> 10) & 3
  2603  		return MemImmediate{Rn, AddrPostIndex, int32(2 << size)}
  2604  
  2605  	case arg_Xns_mem_post_size__3_0__6_1__12_2__24_3:
  2606  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2607  		size := (x >> 10) & 3
  2608  		return MemImmediate{Rn, AddrPostIndex, int32(3 << size)}
  2609  
  2610  	case arg_Xns_mem_post_size__4_0__8_1__16_2__32_3:
  2611  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2612  		size := (x >> 10) & 3
  2613  		return MemImmediate{Rn, AddrPostIndex, int32(4 << size)}
  2614  
  2615  	case arg_Xns_mem_post_Xm:
  2616  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2617  		Rm := (x >> 16) & (1<<5 - 1)
  2618  		return MemImmediate{Rn, AddrPostReg, int32(Rm)}
  2619  
  2620  	case arg_Xns_mem_wb_imm7_16_signed:
  2621  		Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2622  		imm7 := (x >> 15) & (1<<7 - 1)
  2623  		return MemImmediate{Rn, AddrPreIndex, ((int32(imm7 << 4)) << 21) >> 21}
  2624  	}
  2625  }
  2626  
  2627  func handle_ExtendedRegister(x uint32, has_width bool) Arg {
  2628  	s := (x >> 29) & 1
  2629  	rm := (x >> 16) & (1<<5 - 1)
  2630  	option := (x >> 13) & (1<<3 - 1)
  2631  	imm3 := (x >> 10) & (1<<3 - 1)
  2632  	rn := (x >> 5) & (1<<5 - 1)
  2633  	rd := x & (1<<5 - 1)
  2634  	is_32bit := !has_width
  2635  	var rea RegExtshiftAmount
  2636  	if has_width {
  2637  		if option&0x3 != 0x3 {
  2638  			rea.reg = W0 + Reg(rm)
  2639  		} else {
  2640  			rea.reg = X0 + Reg(rm)
  2641  		}
  2642  	} else {
  2643  		rea.reg = W0 + Reg(rm)
  2644  	}
  2645  	switch option {
  2646  	case 0:
  2647  		rea.extShift = uxtb
  2648  	case 1:
  2649  		rea.extShift = uxth
  2650  	case 2:
  2651  		if is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
  2652  			if imm3 != 0 {
  2653  				rea.extShift = lsl
  2654  			} else {
  2655  				rea.extShift = ExtShift(0)
  2656  			}
  2657  		} else {
  2658  			rea.extShift = uxtw
  2659  		}
  2660  	case 3:
  2661  		if !is_32bit && (rn == 31 || (s == 0 && rd == 31)) {
  2662  			if imm3 != 0 {
  2663  				rea.extShift = lsl
  2664  			} else {
  2665  				rea.extShift = ExtShift(0)
  2666  			}
  2667  		} else {
  2668  			rea.extShift = uxtx
  2669  		}
  2670  	case 4:
  2671  		rea.extShift = sxtb
  2672  	case 5:
  2673  		rea.extShift = sxth
  2674  	case 6:
  2675  		rea.extShift = sxtw
  2676  	case 7:
  2677  		rea.extShift = sxtx
  2678  	}
  2679  	rea.show_zero = false
  2680  	rea.amount = uint8(imm3)
  2681  	return rea
  2682  }
  2683  
  2684  func handle_ImmediateShiftedRegister(x uint32, max uint8, is_w, has_ror bool) Arg {
  2685  	var rsa RegExtshiftAmount
  2686  	if is_w {
  2687  		rsa.reg = W0 + Reg((x>>16)&(1<<5-1))
  2688  	} else {
  2689  		rsa.reg = X0 + Reg((x>>16)&(1<<5-1))
  2690  	}
  2691  	switch (x >> 22) & 0x3 {
  2692  	case 0:
  2693  		rsa.extShift = lsl
  2694  	case 1:
  2695  		rsa.extShift = lsr
  2696  	case 2:
  2697  		rsa.extShift = asr
  2698  	case 3:
  2699  		if has_ror {
  2700  			rsa.extShift = ror
  2701  		} else {
  2702  			return nil
  2703  		}
  2704  	}
  2705  	rsa.show_zero = true
  2706  	rsa.amount = uint8((x >> 10) & (1<<6 - 1))
  2707  	if rsa.amount == 0 && rsa.extShift == lsl {
  2708  		rsa.extShift = ExtShift(0)
  2709  	} else if rsa.amount > max {
  2710  		return nil
  2711  	}
  2712  	return rsa
  2713  }
  2714  
  2715  func handle_MemExtend(x uint32, mult uint8, absent bool) Arg {
  2716  	var extend ExtShift
  2717  	var Rm Reg
  2718  	option := (x >> 13) & (1<<3 - 1)
  2719  	Rn := RegSP(X0) + RegSP(x>>5&(1<<5-1))
  2720  	if (option & 1) != 0 {
  2721  		Rm = Reg(X0) + Reg(x>>16&(1<<5-1))
  2722  	} else {
  2723  		Rm = Reg(W0) + Reg(x>>16&(1<<5-1))
  2724  	}
  2725  	switch option {
  2726  	default:
  2727  		return nil
  2728  	case 2:
  2729  		extend = uxtw
  2730  	case 3:
  2731  		extend = lsl
  2732  	case 6:
  2733  		extend = sxtw
  2734  	case 7:
  2735  		extend = sxtx
  2736  	}
  2737  	amount := (uint8((x >> 12) & 1)) * mult
  2738  	return MemExtend{Rn, Rm, extend, amount, absent}
  2739  }
  2740  
  2741  func handle_bitmasks(x uint32, datasize uint8) Arg {
  2742  	var length, levels, esize, i uint8
  2743  	var welem, wmask uint64
  2744  	n := (x >> 22) & 1
  2745  	imms := uint8((x >> 10) & (1<<6 - 1))
  2746  	immr := uint8((x >> 16) & (1<<6 - 1))
  2747  	if n != 0 {
  2748  		length = 6
  2749  	} else if (imms & 32) == 0 {
  2750  		length = 5
  2751  	} else if (imms & 16) == 0 {
  2752  		length = 4
  2753  	} else if (imms & 8) == 0 {
  2754  		length = 3
  2755  	} else if (imms & 4) == 0 {
  2756  		length = 2
  2757  	} else if (imms & 2) == 0 {
  2758  		length = 1
  2759  	} else {
  2760  		return nil
  2761  	}
  2762  	levels = 1<<length - 1
  2763  	s := imms & levels
  2764  	r := immr & levels
  2765  	esize = 1 << length
  2766  	if esize > datasize {
  2767  		return nil
  2768  	}
  2769  	welem = 1<<(s+1) - 1
  2770  	ror := (welem >> r) | (welem << (esize - r))
  2771  	ror &= ((1 << esize) - 1)
  2772  	wmask = 0
  2773  	for i = 0; i < datasize; i += esize {
  2774  		wmask = (wmask << esize) | ror
  2775  	}
  2776  	return Imm64{wmask, false}
  2777  }
  2778  

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